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    • 35. 发明授权
    • High-speed and low-power differential non-volatile content addressable memory cell and array
    • 高速和低功耗差分非易失性内容可寻址存储单元和阵列
    • US07196921B2
    • 2007-03-27
    • US10893811
    • 2004-07-19
    • Vishal SarinHieu Van TranIsao Nojima
    • Vishal SarinHieu Van TranIsao Nojima
    • G11C15/00
    • G11C14/00G11C15/046
    • A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.
    • 差分非易失性内容可寻址存储器阵列具有使用一对非易失性存储元件的差分非易失性内容可寻址存储器单元。 每个非易失性存储元件可以是分离栅极浮栅晶体管或堆叠栅极浮栅晶体管,其具有第一端子,第二端子,其间的沟道以及通道的至少一部分上的浮置栅极以控制 通道中的电子传导,以及控制栅极。 浮置栅极存储晶体管可以处于以下两种状态之一:电流可以在第一端子和第二端子之间流动的第一状态,例如擦除,以及第二状态,诸如编程的,其中基本上没有电流流动 在第一端子和第二端子之间。 一对差分比较数据线连接到该对非易失性浮栅晶体管中的每一个的控制栅极。 匹配线将一对非易失性浮栅晶体管的每一个的第一端连接到第一电压。 最后,每个存储元件的第二端子被连接到与第一电压不同的第二电压。 通过存储单元的电流表示比较数据线的内容与存储元件的内容之间的错误匹配。
    • 36. 发明申请
    • Integrated semiconductor metal-insulator-semiconductor capacitor
    • 集成半导体金属绝缘体 - 半导体电容器
    • US20060017084A1
    • 2006-01-26
    • US10897045
    • 2004-07-22
    • Feng GaoChangyuan ChenVishal SarinWilliam SaikiHieu TranDana Lee
    • Feng GaoChangyuan ChenVishal SarinWilliam SaikiHieu TranDana Lee
    • H01L29/76
    • H01L27/0805H01L27/0811H01L29/94
    • An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.
    • 集成的MIS电容器具有两个基本相同的MIS电容器。 第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。 半导体衬底具有第二导电类型。 栅电极与第一电容器的沟道区隔离并隔开。 第二电容器基本上与第一电容器相同,并且形成在相同的半导体衬底中。 第一电容器的栅电极电连接到第二电容器的第一区域,并且第二电容器的栅极电连接到第一电容器的第一区域。 以这种方式,电容器以反并联配置连接。 具有高电容密度,低工艺复杂性,双极性操作,低电压和温度系数,低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。