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1. 发明授权

US09268899B2 Transistor design for use in advanced nanometer flash memory devices 有权
标题翻译：用于先进纳米闪存器件的晶体管设计
公开(公告)号：US09268899B2
公开(公告)日：2016-02-23
申请号：US13830267
申请日：2013-03-14
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
IPC分类号： G06F17/50 , G11C11/16 , G11C13/00 , G11C16/28
CPC分类号： G11C16/08 , G06F17/5081 , G11C7/062 , G11C8/10 , G11C11/1673 , G11C13/004 , G11C16/26 , G11C16/28
摘要： Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.
摘要翻译：公开了用于高级纳米闪存器件中的感测电路的改进的PMOS和NMOS晶体管设计。

2. 发明授权

US09092044B2 Low voltage, low power bandgap circuit 有权
标题翻译：低电压，低功耗带隙电路
公开(公告)号：US09092044B2
公开(公告)日：2015-07-28
申请号：US13286843
申请日：2011-11-01
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G05F3/02 , G05F3/30
CPC分类号： G05F3/30
摘要： A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.
摘要翻译：用于产生带隙电压的带隙电压产生电路具有具有两个输入和输出的运算放大器。电流镜电路具有至少两个平行电流路径。每个电流路径由运算放大器的输出控制。电流路径之一耦合到运算放大器的两个输入之一。电阻分压电路连接到另一个电流通路。电阻分压电路提供电路的带隙电压。

3. 发明授权

US08975131B2 Self-aligned method of forming a semiconductor memory array of floating gate memory cells with single poly layer 有权
标题翻译：用单层多层形成浮栅存储器单元的半导体存储器阵列的自对准方法
公开(公告)号：US08975131B2
公开(公告)日：2015-03-10
申请号：US13631474
申请日：2012-09-28
申请人： Nhan Do , Vipin Tiwari , Hieu Van Tran , Xian Liu
发明人： Nhan Do , Vipin Tiwari , Hieu Van Tran , Xian Liu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , H01L29/0847 , H01L29/42324 , H01L29/66825
摘要： A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.
摘要翻译：一种形成半导体存储单元的方法，包括从同一多晶层形成浮置和控制栅极。在衬底上形成绝缘层，导电和第二绝缘材料层。在第二绝缘材料中形成沟槽，其向下延伸并暴露导电层。间隔件形成在沟槽中，由沟槽底部的小的和限定的间隙隔开，该间隙露出导电层的一部分。然后通过穿过间隙进行各向异性蚀刻，通过导电层的暴露部分形成沟槽。沟槽填充有第三绝缘材料。去除导电层的选定部分，留下两个由第三绝缘材料隔开的块。

4. 发明申请

US20140104965A1 Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming 有权
标题翻译：非易失性存储器阵列及使用相同的分数字编程方法
公开(公告)号：US20140104965A1
公开(公告)日：2014-04-17
申请号：US13652447
申请日：2012-10-15
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C8/08 , G11C11/5628 , G11C16/08 , G11C16/10
摘要： A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.
摘要翻译：包括非易失性存储器单元的N个平面（其中N是大于1的整数）的非易失性存储器件。非易失性存储单元的每个平面包括以行和列配置的多个存储器单元。 N平面中的每一个包括在其中存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线。控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并根据因子反向改变程序时间段。

5. 发明授权

US08693274B2 Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features 有权
标题翻译：非易失性存储器感测的系统和方法包括选择性/差分阈值电压特征
公开(公告)号：US08693274B2
公开(公告)日：2014-04-08
申请号：US13776690
申请日：2013-02-25
申请人： Hieu Van Tran , Samar Saha
发明人： Hieu Van Tran , Samar Saha
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C16/28 , H01L21/28282 , H01L21/823412 , H01L21/823807 , H01L29/1083 , H01L29/42368 , H01L29/4238 , H01L29/66833 , H01L29/7835 , H01L29/792
摘要： Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.
摘要翻译：公开了用于通过使用具有差分阈值电压的MOS晶体管来提供选择性阈值电压特性的系统和方法。在一个示例性实施例中，提供了一种金属氧化物半导体器件，其包括半导体材料的衬底，其具有源极区，漏极区和它们之间的沟道区，沟道区上方的绝缘层和绝缘层的栅极部。此外，关于器件，绝缘层的形状和/或接合区域的形状或注入在栅极 - 漏极和栅极 - 源极结之间具有不同的尺寸，以提供不同的阈值电压他们。

6. 发明授权

US08565038B2 Power line compensation for flash memory sense amplifiers 有权
标题翻译：闪存读出放大器的电源线补偿
公开(公告)号：US08565038B2
公开(公告)日：2013-10-22
申请号：US12766682
申请日：2010-04-23
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/147 , G11C7/02 , G11C7/06 , G11C7/065 , G11C7/067 , G11C11/4091 , G11C11/5642 , G11C16/28 , G11C16/30 , G11C2207/063 , G11C2211/5645
摘要： In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
摘要翻译：一方面，本发明涉及一种用于补偿多电平存储器的读出放大器中的功率电平变化的存储器系统。例如，可以采用补偿电路来补偿提供给多电平存储器读出放大器的功率的电流或电压变化。作为另一示例，可以通过向电源施加偏置电压来实现补偿。另一个例子是配置有改进的输入共模电压范围的读出放大器。这样的读出放大器可以是两对和三对读出放大器。本发明的其它示例包括更简化的读出放大器配置和具有减小的漏电流的读出放大器。

7. 发明授权

US08513728B2 Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates 有权
标题翻译：阵列的分离栅极非易失性浮动栅极存储单元具有改进的耦合栅极的捆扎
公开(公告)号：US08513728B2
公开(公告)日：2013-08-20
申请号：US13299320
申请日：2011-11-17
申请人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
发明人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
IPC分类号： H01L29/788
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.
摘要翻译：具有在行方向上延伸的具有间隔开的第一区域和在列方向上延伸的第二区域的非易失性存储器单元的阵列，其中限定在每个第二区域与其相关联的第一区域之间的通道区域。每个在行方向上延伸并定位在通道区域的第一部分上方的多个间隔开的字线门。多个间隔开的浮动栅极位于沟道区域的第二部分上方。多个间隔开的耦合栅极，每个在行方向和浮动栅极上延伸。多个间隔开的金属捆绑线，各自在行方向上延伸并且覆盖耦合门。多个间隔开的擦除栅极，每个沿行方向延伸并定位在第一区域上并且与浮栅和耦合栅极相邻。

8. 发明授权

US08432750B2 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US08432750B2
公开(公告)日：2013-04-30
申请号：US12961458
申请日：2010-12-06
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

9. 发明授权

US08300494B2 Sub volt flash memory system 有权
标题翻译：亚伏闪存系统
公开(公告)号：US08300494B2
公开(公告)日：2012-10-30
申请号：US12980209
申请日：2010-12-28
申请人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
发明人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C16/28 , G11C16/08 , G11C16/30
摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
摘要翻译：各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。电路可以包括在存储器系统中。

10. 发明授权

US08232833B2 Charge pump systems and methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US08232833B2
公开(公告)日：2012-07-31
申请号：US11805765
申请日：2007-05-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F3/24 , H02M3/18
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

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