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31. 发明申请

US20120168931A1 CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES 有权
标题翻译：用于增强半导体模块散热的碳纳米管结构
公开(公告)号：US20120168931A1
公开(公告)日：2012-07-05
申请号：US13418454
申请日：2012-03-13
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , Charles W. Koburger, III , Krishna V. Singh
IPC分类号： H01L23/36 , H01L21/50 , B82Y99/00 , B82Y40/00
CPC分类号： H01L23/373 , B82Y10/00 , B82Y40/00 , H01L21/6835 , H01L23/3157 , H01L23/433 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2221/6835 , H01L2221/68377 , H01L2224/0401 , H01L2224/05026 , H01L2224/05186 , H01L2224/05561 , H01L2224/05564 , H01L2224/05571 , H01L2224/05655 , H01L2224/05657 , H01L2224/0566 , H01L2224/10135 , H01L2224/113 , H01L2224/11845 , H01L2224/13021 , H01L2224/13076 , H01L2224/131 , H01L2224/13147 , H01L2224/13184 , H01L2224/13187 , H01L2224/13193 , H01L2224/16221 , H01L2224/1703 , H01L2224/17515 , H01L2224/274 , H01L2224/73253 , H01L2224/81139 , H01L2224/81191 , H01L2224/81193 , H01L2224/81493 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/04953 , H01L2224/05552
摘要： Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.
摘要翻译：公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

32. 发明申请

US20090255818A1 METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS 有权
标题翻译：用于监测雕刻开口的完整性和形成具有开口的导电结构的方法
公开(公告)号：US20090255818A1
公开(公告)日：2009-10-15
申请号：US12101329
申请日：2008-04-11
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L21/288
CPC分类号： H01L21/76879 , C25D5/10 , C25D5/12 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76802 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.
摘要翻译：公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等）。）在这样的开口内。该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。

33. 发明申请

US20090032491A1 CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER 审中-公开
标题翻译：使用形成介质层的真实层形成的导电元件
公开(公告)号：US20090032491A1
公开(公告)日：2009-02-05
申请号：US11833301
申请日：2007-08-03
申请人： Veeraraghavan S. Basker , Steven J. Holmes , David V. Horak , Muthumanickam Sankarapandian
发明人： Veeraraghavan S. Basker , Steven J. Holmes , David V. Horak , Muthumanickam Sankarapandian
IPC分类号： H01B13/00 , B32B3/10
CPC分类号： H01L21/76808 , H01L21/76802 , H01L2221/1026 , H01L2221/1031 , Y10T428/24273
摘要： Methods of forming a conductive element for an integrated circuit (IC) chip and a related structure are disclosed. One embodiment of the method may include forming a first sacrificial layer having a pattern therein for a first dielectric layer to surround the conductive element; forming the first dielectric layer within the patterned first sacrificial layer; removing the patterned first sacrificial layer, leaving the first dielectric layer; and forming the conductive element in a space vacated by the patterned first sacrificial layer. The methods prevent damage caused to low dielectric constant dielectric layers during etching and stripping/cleaning processes.
摘要翻译：公开了形成用于集成电路（IC）芯片的导电元件和相关结构的方法。该方法的一个实施例可以包括形成其中具有图案的第一牺牲层用于第一介电层以围绕导电元件; 在所述图案化的第一牺牲层内形成所述第一介电层; 去除图案化的第一牺牲层，留下第一介电层; 以及在由图案化的第一牺牲层腾出的空间中形成导电元件。该方法防止在蚀刻和剥离/清洗过程中对低介电常数电介质层造成的损坏。

34. 发明授权

US09620619B2 Borderless contact structure 有权
公开(公告)号：US09620619B2
公开(公告)日：2017-04-11
申请号：US13348894
申请日：2012-01-12
申请人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/20 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/66628 , H01L29/78
摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

35. 发明授权

US08723262B2 SOI FinFET with recessed merged fins and liner for enhanced stress coupling 有权
标题翻译： SOI FinFET具有凹入的合并翅片和衬垫，用于增强应力耦合
公开(公告)号：US08723262B2
公开(公告)日：2014-05-13
申请号：US13606893
申请日：2012-09-07
申请人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Huiming Bu , Effendi Leobandung , Theodorus E. Standaert , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7843 , H01L29/6656 , H01L29/66795
摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.
摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷。然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。垂直硅化物提高了耐扩散性。

36. 发明申请

US20140087526A1 MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES 审中-公开
标题翻译：多门场效应晶体管器件
公开(公告)号：US20140087526A1
公开(公告)日：2014-03-27
申请号：US13628251
申请日：2012-09-27
申请人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method for fabricating a field effect transistor device includes patterning a semiconductor fin on a substrate insulator layer, the substrate insulator layer arranged on a substrate, patterning a dummy gate stack over a portion of the fin, forming spacers adjacent to the dummy gate stack, removing the dummy gate stack to form a cavity that exposes portions of the substrate insulator layer and the fin, removing exposed portions of the substrate insulator layer to increase a depth of the cavity, removing a region of the substrate insulator layer from beneath the fin to suspend a portion of the fin above the substrate insulator layer, forming a gate stack in the cavity, removing a portion of the gate stack in the cavity to expose a portion of a dielectric layer arranged on the fin, and depositing an insulator material in the cavity.
摘要翻译：一种用于制造场效应晶体管器件的方法，包括在衬底绝缘体层上图形化半导体鳍片，将衬底绝缘体层布置在衬底上，在鳍片的一部分上构图虚拟栅极堆叠，形成与虚拟栅极叠层相邻的间隔区，去除虚拟栅极堆叠以形成露出衬底绝缘体层和鳍的部分的空腔，去除衬底绝缘体层的暴露部分以增加空腔的深度，从衬底下方去除衬底绝缘体层的区域到悬挂在衬底绝缘体层上方的鳍片的一部分，在空腔中形成栅极叠层，去除空腔中的栅极叠层的一部分以暴露布置在鳍片上的电介质层的一部分，并将绝缘体材料沉积在腔。

37. 发明授权

US08674476B2 Anti-fuse device structure and electroplating circuit structure and method 有权
标题翻译：反熔丝器件结构及电镀电路结构及方法
公开(公告)号：US08674476B2
公开(公告)日：2014-03-18
申请号：US13535393
申请日：2012-06-28
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译：公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。在电沉积期间，可以选择性地控制通过电流路径的电流。此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

38. 发明申请

US20140070294A1 FINFET TRENCH CIRCUIT 有权
标题翻译： FINFET TRENCH电路
公开(公告)号：US20140070294A1
公开(公告)日：2014-03-13
申请号：US13613684
申请日：2012-09-13
申请人： Jonathan E. Faltermeier , Veeraraghavan S. Basker , Kangguo Cheng , Theodorus Eduardus Standaert
发明人： Jonathan E. Faltermeier , Veeraraghavan S. Basker , Kangguo Cheng , Theodorus Eduardus Standaert
IPC分类号： H01L27/12 , H01L21/02
CPC分类号： H01L27/10829 , H01L21/845 , H01L27/10826 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/10879 , H01L27/1207 , H01L27/1211 , H01L29/66181 , H01L29/945
摘要： A finFET trench circuit is disclosed. FinFETs are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor. A passing gate is then disposed over the trench top oxide to form a larger circuit, such as a DRAM array. The trench top oxide is formed by utilizing different growth rates between polysilicon and single crystal silicon.
摘要翻译：公开了一种finFET沟槽电路。 FinFET通过在沟槽导体的一部分上采用沟槽顶部氧化物与沟槽电容器集成。然后将通过栅极设置在沟槽顶部氧化物上方以形成更大的电路，例如DRAM阵列。通过利用多晶硅和单晶硅之间的不同生长速率形成沟槽顶部氧化物。

39. 发明授权

US08592290B1 Cut-very-last dual-EPI flow 有权
标题翻译：切割最后的双EPI流程
公开(公告)号：US08592290B1
公开(公告)日：2013-11-26
申请号：US13545456
申请日：2012-07-10
申请人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
发明人： Veeraraghavan S. Basker , Huiming Bu , Kangguo Cheng , Balasubramanian S. Haran , Nicolas Loubet , Shom Ponoth , Stefan Schmitz , Theodorus E. Standaert , Tenko Yamashita
IPC分类号： H01L21/20
CPC分类号： H01L29/66795 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/6681
摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.
摘要翻译：描述了制造双外延FinFET的方法。该方法包括将第一外延材料添加到翅片阵列。该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。还描述了装置和计算机程序产品。

40. 发明申请

US20130175594A1 INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC 有权
公开(公告)号：US20130175594A1
公开(公告)日：2013-07-11
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

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