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31. 发明授权

US08246366B2 Electrical card connector with a stop member for temporarily preventing a card from ejecting from the card release position 有权
标题翻译：具有用于暂时防止卡从卡释放位置弹出的止动构件的电子卡连接器
公开(公告)号：US08246366B2
公开(公告)日：2012-08-21
申请号：US13036055
申请日：2011-02-28
申请人： Tzu-Ching Tsai , Kai-Li Wang
发明人： Tzu-Ching Tsai , Kai-Li Wang
IPC分类号： H01R13/62
CPC分类号： G06K13/08
摘要： An electrical card connector includes an insulative housing, a number of contacts and a push-push mechanism. The push-push mechanism includes a slider, an elastic member for driving the slider and a locking arm fixed to the slider. The locking arm includes a hook protruding into a card receiving space for locking with the card when the card is fully inserted into the card receiving space at a card locking position. When the card is ejected under a normal speed, the locking arm can be outwardly deformed to disengage from the card at a card release position. When the card is ejected under an abnormal speed faster than the normal speed, the slider gets over the card release position where the locking arm is restricted by a stop member to prevent the hook from releasing the card.
摘要翻译：电卡连接器包括绝缘壳体，多个触点和推 - 推机构。推动机构包括滑块，用于驱动滑块的弹性构件和固定到滑块的锁定臂。当卡在卡锁定位置完全插入卡容纳空间时，锁定臂包括突出到卡接收空间中的钩子，用于与卡锁定。当卡以正常速度弹出时，锁定臂可以向外变形以在卡释放位置脱离卡。当卡片以比正常速度快的异常速度弹出时，滑块越过卡片释放位置，锁定臂被止动构件限制，以防止钩子释放卡片。

32. 发明授权

US07980870B2 Electrical card connector 失效
标题翻译：电卡连接器
公开(公告)号：US07980870B2
公开(公告)日：2011-07-19
申请号：US12842079
申请日：2010-07-23
申请人： Chang-Hsien Tung , Tzu-Ching Tsai , Kai-Li Wang
发明人： Chang-Hsien Tung , Tzu-Ching Tsai , Kai-Li Wang
IPC分类号： H01R13/62
CPC分类号： H01R27/00 , G06K13/08 , H01R12/721 , H01R13/6581
摘要： An electrical card connector (100) includes an insulative housing (10) defining a card receiving room, at least one set of terminals (30) retained in the insulative housing, and an ejector attached on the insulative housing. Each terminal has a soldering portion (303) extending out of the insulative housing and a contacting portion (301) extending towards the card receiving room. The ejector includes a slider (50), at least one spring member (90) and at least one pin member (80) cammedly pushing an inserted card. The slider includes a base portion (501) pressing against the contacting portions of the terminals and a pair of arm portions (503) extending laterally from the base portion. The base portion defines a number of passageways (502) and forms a number of protrusions (5011) extending into the corresponding passageways. The slider blocks the contacting portions from entering the card receiving room at an original position and moves to an inner position for giving way for the contacting portions. The contacting portions extend through the passageways into the card receiving room are supported by the protrusions.
摘要翻译：电卡连接器（100）包括限定卡接收室的绝缘壳体（10），保持在绝缘壳体中的至少一组端子（30）和连接在绝缘壳体上的喷射器。每个端子具有从绝缘壳体延伸出的焊接部分（303）和朝向卡接收室延伸的接触部分（301）。喷射器包括滑块（50），至少一个弹簧构件（90）和至少一个销构件（80），凸出地推动插入的卡。滑块包括：压靠端子的接触部分的基部（501）和从基部侧向延伸的一对臂部（503）。基部限定多个通道（502）并形成延伸到相应通道中的多个突起（5011）。滑块阻止接触部分在原始位置进入卡接收室，并移动到用于接触部分的通路的内部位置。接触部分延伸通过插入卡片容纳室的通道由突起支撑。

33. 发明授权

US07807558B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07807558B2
公开(公告)日：2010-10-05
申请号：US11933732
申请日：2007-11-01
申请人： Tzu-Ching Tsai , Tse-Yao Huang , Yi-Nan Chen
发明人： Tzu-Ching Tsai , Tse-Yao Huang , Yi-Nan Chen
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02063 , H01L21/02071 , H01L21/32137
摘要： A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide.
摘要翻译：提供一种制造半导体器件的方法。制造半导体器件的方法包括提供衬底。接下来，依次在基板上形成绝缘层，导电层和硅化物层。接下来，在暴露硅化物层的一部分的硅化物层上形成硬掩模层。执行第一蚀刻步骤以去除未被硬掩模层覆盖的硅化物层和下面的导电层，从而形成栅极堆叠。接下来，执行第二蚀刻步骤以在第一蚀刻步骤之后去除未被硬掩模层覆盖的剩余导电层。用包含氢氧化铵的蚀刻剂进行第二蚀刻步骤。

34. 发明申请

US20080119071A1 Electrical card connector 失效
标题翻译：电卡连接器
公开(公告)号：US20080119071A1
公开(公告)日：2008-05-22
申请号：US11986194
申请日：2007-11-20
申请人： Chien-Jen Ting , Tzu-Ching Tsai
发明人： Chien-Jen Ting , Tzu-Ching Tsai
IPC分类号： H01R12/14
CPC分类号： H01R12/7029 , H01R13/6595
摘要： An electrical card connector includes a metal shield (2), an insulated housing (3) and a terminal module (4). The metal shield defines a receiving room, in which a memory card is insertable in a card inserting direction through an insert opening generally at a front end thereof. The insulated housing is shielded by the metal shield, and defines a receiving portion (34) extending therethrough and adjacent to a rear end thereof. The terminal module is received in the receiving portion of the insulated housing and comprises a pair of locking boards (44) assembling the terminal module on a printed circuit board (5). A plurality of terminals (31) are insert-molded in the terminal module for electrical connection to the memory card.
摘要翻译：电卡连接器包括金属屏蔽（2），绝缘外壳（3）和端子模块（4）。金属屏蔽限定了接收室，其中存储卡可以通过大致在其前端处的插入开口插入卡插入方向。绝缘壳体被金属屏蔽件屏蔽，并且限定了延伸穿过其并与其后端相邻的接收部分（34）。端子模块被容纳在绝缘壳体的接收部分中，并且包括将终端模块组装在印刷电路板（5）上的一对锁定板（44）。多个端子（31）被插入模制在端子模块中以与存储卡电连接。

35. 发明申请

US20070020844A1 Method for fabricating bit line of memory device 审中-公开
标题翻译：存储器件位线的制造方法
公开(公告)号：US20070020844A1
公开(公告)日：2007-01-25
申请号：US11490206
申请日：2006-07-19
申请人： Yi-Nan Chen , Tzu-Ching Tsai
发明人： Yi-Nan Chen , Tzu-Ching Tsai
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L27/10888 , H01L27/10885
摘要： A damascene process. A substrate covered by a dielectric layer and an overlying polysilicon masking layer with an opening exposing the underlying dielectric layer is provided. The exposed dielectric layer is etched to form a damascene opening therein and a portion of polysilicon masking layer remains on the dielectric layer. The remaining polysilicon masking layer is completely transformed into a metal polycide layer and then removed. A method for fabricating a bit line of a memory device is also disclosed.
摘要翻译：一个镶嵌过程。提供了由电介质层覆盖的衬底和具有暴露下面介电层的开口的上覆多晶硅掩模层。蚀刻暴露的介电层以在其中形成镶嵌开口，并且一部分多晶硅掩模层保留在电介质层上。剩余的多晶硅掩模层完全转变为金属多晶硅化物层，然后除去。还公开了一种用于制造存储器件的位线的方法。

36. 发明授权

US07026207B2 Method of filling bit line contact via 有权
标题翻译：填充位线接触的方法
公开(公告)号：US07026207B2
公开(公告)日：2006-04-11
申请号：US10715611
申请日：2003-11-18
申请人： Tzu-Ching Tsai , Yi-Nan Chen
发明人： Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： H01L21/8238
CPC分类号： H01L27/10888 , H01L21/76877 , H01L27/10894
摘要： A method of filling a bit line contact via. The method includes providing a substrate having a device region and periphery region, the device region having a transistor, having a gate electrode, drain region, and source region, on the substrate, forming a dielectric layer overlying the substrate, the dielectric layer having a bit line contact via exposing the drain region, and periphery contact via exposing the periphery region, forming a doped conductive layer, lower than the dielectric layer, overlying the drain region, conformally forming a barrier layer overlying the dielectric layer, doped conductive layer, and periphery region, and forming a first conductive layer filling the bit line contact via and periphery contact via.
摘要翻译：填充位线接触通孔的方法。该方法包括提供具有器件区域和外围区域的衬底，器件区域具有在衬底上的栅电极，漏极区和源极区的晶体管，形成覆盖衬底的电介质层，电介质层具有通过暴露漏极区域和周边接触，通过暴露外围区域形成位线接触，形成覆盖漏极区域的低于介电层的掺杂导电层，保形地形成覆盖在电介质层上的阻挡层，掺杂导电层和并且形成填充位线接触通孔和周边接触通孔的第一导电层。

37. 发明授权

US06946344B2 Method for forming trench capacitor 有权
标题翻译：形成沟槽电容器的方法
公开(公告)号：US06946344B2
公开(公告)日：2005-09-20
申请号：US10620743
申请日：2003-07-16
申请人： Shih-Chung Chou , Yi-Nan Chen , Tzu-Ching Tsai
发明人： Shih-Chung Chou , Yi-Nan Chen , Tzu-Ching Tsai
IPC分类号： H01L21/00 , H01L21/20 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/1087 , Y10T29/41
摘要： A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to form an ion doped area on a sidewall of the top portion of the trench and a top surface of the trench capacitor. The ion doped area is oxidized to form an oxide layer. A sidewall semiconductor layer is formed on another sidewall using the oxide layer as a mask, and then the oxide layer is removed. A barrier layer is conformally formed on the surface of the trench, and the trench is filled with a conducting layer.
摘要翻译：一种形成沟槽电容器的方法。提供具有沟槽的半导体衬底，并且沟槽电容器在沟槽中形成有存储节点和节点电介质层。将沟槽的顶部离子注入预定角度，以在沟槽顶部的侧壁和沟槽电容器的顶表面上形成离子掺杂区域。离子掺杂区域被氧化形成氧化物层。使用氧化物层作为掩模在另一侧壁上形成侧壁半导体层，然后除去氧化物层。在沟槽的表面上保形地形成阻挡层，并且沟槽填充有导电层。

38. 发明授权

US06852590B1 Deep trench capacitor and method of fabricating the same 有权
标题翻译：深沟槽电容器及其制造方法
公开(公告)号：US06852590B1
公开(公告)日：2005-02-08
申请号：US10709926
申请日：2004-06-07
申请人： Tzu-Ching Tsai , Shih-Chung Chou
发明人： Tzu-Ching Tsai , Shih-Chung Chou
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A method of fabricating a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped region is formed in the substrate at the bottom of the deep trench, a dielectric layer is formed on the bottom surface of the deep trench, and a first conductive layer is formed on the dielectric layer. A collar oxide layer is formed on sidewalls of the deep trench that are not covered by the first conductive layer. A material layer is formed covering the first conductive layer and exposing a portion of the collar oxide layer. The exposed collar oxide layer is removed to expose the substrate. Then, the material layer is removed, and a second conductive layer is formed in the deep trench covering the first conductive layer and the collar oxide layer. In this invention, only the second conductive layer is formed on the first conductive layer for electrically connecting the capacitor and an active device, hence the method is more simple.
摘要翻译：描述制造深沟槽电容器的方法。提供其中具有深沟槽的衬底。在深沟槽的底部的衬底中形成掺杂区域，在深沟槽的底表面上形成介电层，并且在介电层上形成第一导电层。在深沟槽的不被第一导电层覆盖的侧壁上形成环状氧化物层。形成覆盖第一导电层并暴露套环氧化物层的一部分的材料层。去除暴露的环状氧化物层以暴露衬底。然后，去除材料层，并且在覆盖第一导电层和套环氧化物层的深沟槽中形成第二导电层。在本发明中，仅在第一导电层上形成第二导电层，用于电连接有源器件，因此该方法更简单。

39. 发明授权

US06815307B1 Method for fabricating a deep trench capacitor 有权
标题翻译：深沟槽电容器的制造方法
公开(公告)号：US06815307B1
公开(公告)日：2004-11-09
申请号：US10605217
申请日：2003-09-16
申请人： Ping Hsu , Tzu-Ching Tsai
发明人： Ping Hsu , Tzu-Ching Tsai
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181
摘要： This invention pertains to a method for making a trench capacitor of DRAM devices. A portion of the collar oxide layer is masked after the second polysilicon deposition and recess etching process. Subsequently, the un-masked collar oxide layer is etched away to form an asymmetric collar oxide structure. The third polysilicon deposition and recess etching process is then carried out to form a third polysilicon stud atop the second polysilicon layer. The asymmetric collar oxide structure has a lower annular portion wrapping the second polysilicon layer and insulating the second polysilicon layer from the substrate, and an upper portion serving as a single-sided spacer for blocking diffusion of dopants from the third polysilicon stud to the substrate.

40. 发明授权

US06383936B1 Method for removing black silicon in semiconductor fabrication 有权
标题翻译：在半导体制造中去除黑色硅的方法
公开(公告)号：US06383936B1
公开(公告)日：2002-05-07
申请号：US09875908
申请日：2001-06-08
申请人： Tzu-Ching Tsai , Hung-Hsin Lin
发明人： Tzu-Ching Tsai , Hung-Hsin Lin
IPC分类号： H01L2100
CPC分类号： H01L21/30604 , H01L21/3065 , H01L21/3083 , H01L27/1087
摘要： A method for removing black silicon in semiconductor fabrication is disclosed. First, a trench is formed in a semiconductor substrate having a pad dielectric layer and a hard mask layer. Then, the hard mask layer is removed. A photoresist layer covers the trench and only black silicon created at the edge of the semiconductor substrate during formation of the trench is left uncovered. Finally, the black silicon is removed.
摘要翻译：公开了一种在半导体制造中去除黑硅的方法。首先，在具有焊盘电介质层和硬掩模层的半导体衬底中形成沟槽。然后，去除硬掩模层。光致抗蚀剂层覆盖沟槽，并且在形成沟槽期间仅在半导体衬底的边缘处产生的黑色硅未被覆盖。最后，黑硅被去除。

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