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31. 发明授权

US08251723B2 Interconnection system incorporated with magnetic arrangement 有权
标题翻译：互连系统结合磁排列
公开(公告)号：US08251723B2
公开(公告)日：2012-08-28
申请号：US12773027
申请日：2010-05-04
申请人： Tzu-Ching Tsai
发明人： Tzu-Ching Tsai
IPC分类号： H01R27/00
CPC分类号： H01R24/38 , H01R13/2421 , H01R2103/00
摘要： An electrical connector assembly includes a first connector and a second connector each defining a mating end of a regular polygon mating with each other. Each regular polygon defines a center, an imaginary circle around the center and a plurality of vertices at the imaginary circle. A plurality of pins are located at the mating ends which composed of one first pin at the center of the first connector, two second pins at least fulfilling with one half of the vertices and arranged at adjacent vertices in turn, one third pin at the center of the second connector and two forth pins at the vertices respectively in a condition that said two forth pins spaced from each other with a largest distance.
摘要翻译：电连接器组件包括第一连接器和第二连接器，每个连接器和第二连接器限定彼此配合的正多边形的配合端。每个正多边形定义中心，围绕中心的假想圆和在假想圆处的多个顶点。多个销位于配合端，由第一连接器中心的一个第一销组成，两个第二销至少满足顶点的一半，依次布置在相邻的顶点处，中心位置为第三个销钉的第二连接器和两个第四针在顶点处，分别处于所述两个第二引脚彼此间隔最大的条件下。

32. 外观设计

USD611419S1 Electrical connector 有权
公开(公告)号：USD611419S1
公开(公告)日：2010-03-09
申请号：US29310952
申请日：2008-09-19
申请人： Tzu-Ching Tsai , Ren-Chih Li
设计人： Tzu-Ching Tsai , Ren-Chih Li

33. 外观设计

USD603797S1 Electrical connector 有权
公开(公告)号：USD603797S1
公开(公告)日：2009-11-10
申请号：US29310951
申请日：2008-09-19
申请人： Tzu-Ching Tsai , Ren-Chih Li
设计人： Tzu-Ching Tsai , Ren-Chih Li

34. 发明申请

US20090053939A1 Electrical connector having improved contacts therein 有权
标题翻译：电连接器具有改善的接触
公开(公告)号：US20090053939A1
公开(公告)日：2009-02-26
申请号：US12229643
申请日：2008-08-25
申请人： Tzu-Ching Tsai
发明人： Tzu-Ching Tsai
IPC分类号： H01R13/10 , H01R13/02 , H01R24/00
CPC分类号： H01R12/716 , H01R12/57 , H01R13/115 , H01R13/41
摘要： An electrical connector mounted on a PCB (printed circuit board) includes an insulating housing having a receiving room and a plurality of contacts retained in the insulating housing. Said insulating housing has a tongue portion and a peripheral wall surrounds said tongue portion which defines said receiving room. Each contact includes a U-shaped contacting portion received in said receiving room, a vertical holding portion retained in an inner surface of said peripheral wall and a connecting portion connecting with said contacting portion and said holding portion. Said connecting portion has a linear leading surface which is formed slanted towards said contacting portion downwardly in order to provide a smooth mating process with a mating connector.
摘要翻译：安装在PCB（印刷电路板）上的电连接器包括具有容纳室的绝缘壳体和保持在绝缘壳体中的多个触点。所述绝缘壳体具有舌部和围绕限定所述接收室的所述舌部的周壁。每个触点包括容纳在所述容纳室中的U形接触部分，保持在所述周壁的内表面中的垂直保持部分和与所述接触部分和所述保持部分连接的连接部分。所述连接部分具有向下朝向所述接触部分倾斜地形成的线性前导表面，以便与配合连接器提供平滑的配合过程。

35. 外观设计

USD587208S1 Electrical connector 有权
公开(公告)号：USD587208S1
公开(公告)日：2009-02-24
申请号：US29308587
申请日：2008-06-23
申请人： Tzu-Ching Tsai , Ren-Chih Li
设计人： Tzu-Ching Tsai , Ren-Chih Li

36. 发明申请

US20060127680A1 Multi-layer hard mask structure for etching deep trench in substrate 有权
公开(公告)号：US20060127680A1
公开(公告)日：2006-06-15
申请号：US11348626
申请日：2006-02-07
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： B32B17/06 , B32B9/00
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

37. 发明授权

US07029753B2 Multi-layer hard mask structure for etching deep trench in substrate 有权
标题翻译：用于蚀刻衬底深沟槽的多层硬掩模结构
公开(公告)号：US07029753B2
公开(公告)日：2006-04-18
申请号：US10727790
申请日：2003-12-04
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： B23B17/06
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
摘要翻译：一种用于蚀刻衬底中的深沟槽的方法。形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。去除多层硬掩模结构。

38. 发明授权

US06964926B2 Method of forming geometric deep trench capacitors 有权
标题翻译：形成几何深沟槽电容器的方法
公开(公告)号：US06964926B2
公开(公告)日：2005-11-15
申请号：US10727924
申请日：2003-12-04
申请人： Tse-Yao Huang , Yi-Nan Chen , Tzu-Ching Tsai
发明人： Tse-Yao Huang , Yi-Nan Chen , Tzu-Ching Tsai
IPC分类号： H01L21/20 , H01L21/308 , H01L21/334 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/66181 , Y10S438/942
摘要： A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.
摘要翻译：一种形成具有几何深沟槽的电容器的方法。首先，提供在其上形成有衬垫结构的衬底，并且在衬垫结构上形成第一硬掩模层。接着，在第一硬掩模层上形成第二硬掩模层。接下来，在第一硬掩模层上的第一开口中形成间隔层以露出第二开口。接下来，在第二开口填充第三硬掩模层，并且移除间隔层。接下来，第一硬掩模层被蚀刻以暴露具有第一硬掩模层的凸起的第三开口，第二硬掩模层和第三硬掩模层用作掩模。最后，蚀刻第一硬掩模层，焊盘结构和衬底以形成几何深沟槽。

39. 发明申请

US20050042871A1 Multi-layer hard mask structure for etching deep trench in substrate 有权
标题翻译：用于蚀刻衬底深沟槽的多层硬掩模结构
公开(公告)号：US20050042871A1
公开(公告)日：2005-02-24
申请号：US10727790
申请日：2003-12-04
申请人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
发明人： Kaan-Lu Tzou , Tzu-Ching Tsai , Yi-Nan Chen
IPC分类号： C03C15/00 , H01L21/033 , H01L21/308 , H01L21/8242 , B32B17/06 , H01L21/302 , H01L21/461
CPC分类号： H01L27/1087 , C03C15/00 , H01L21/0332 , H01L21/3081
摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
摘要翻译：一种用于蚀刻衬底中的深沟槽的方法。形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。去除多层硬掩模结构。

40. 发明授权

US06225186B1 Method for fabricating LOCOS isolation 有权
标题翻译： LOCOS隔离制造方法
公开(公告)号：US06225186B1
公开(公告)日：2001-05-01
申请号：US09227092
申请日：1999-01-05
申请人： Lin-Chin Su , Tzu-Ching Tsai , Minn-Jiunn Jiang
发明人： Lin-Chin Su , Tzu-Ching Tsai , Minn-Jiunn Jiang
IPC分类号： H01L2176
CPC分类号： H01L21/76205
摘要： A method for fabricating a LOCOS isolation in accordance with the present invention, involves first forming a masking layer on the active region of a silicon substrate. Next, the masking layer is used as the etching mask and the silicon substrate is etched to form a recess. Then, a thin nitride layer is formed on the masking layer and the recess. Afterwards, a polysilicon layer is deposited on the thin nitride layer. Then, an etching process is applied to etch back the polysilicon and the thin nitride layer, thereby exposing the upper surface of the masking layer. Next, a LOCOS isolation is grown above the recess.
摘要翻译：根据本发明的用于制造LOCOS隔离的方法包括首先在硅衬底的有源区上形成掩模层。接下来，使用掩模层作为蚀刻掩模，并蚀刻硅衬底以形成凹部。然后，在掩模层和凹部上形成薄的氮化物层。之后，在薄氮化物层上沉积多晶硅层。然后，施加蚀刻工艺来蚀刻多晶硅和薄氮化物层，从而暴露掩模层的上表面。接下来，在凹部上方生长LOCOS隔离。

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