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    • 1. 发明授权
    • Method for forming trench capacitor
    • 形成沟槽电容器的方法
    • US06946344B2
    • 2005-09-20
    • US10620743
    • 2003-07-16
    • Shih-Chung ChouYi-Nan ChenTzu-Ching Tsai
    • Shih-Chung ChouYi-Nan ChenTzu-Ching Tsai
    • H01L21/00H01L21/20H01L21/8242
    • H01L27/10861H01L27/1087Y10T29/41
    • A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to form an ion doped area on a sidewall of the top portion of the trench and a top surface of the trench capacitor. The ion doped area is oxidized to form an oxide layer. A sidewall semiconductor layer is formed on another sidewall using the oxide layer as a mask, and then the oxide layer is removed. A barrier layer is conformally formed on the surface of the trench, and the trench is filled with a conducting layer.
    • 一种形成沟槽电容器的方法。 提供具有沟槽的半导体衬底,并且沟槽电容器在沟槽中形成有存储节点和节点电介质层。 将沟槽的顶部离子注入预定角度,以在沟槽顶部的侧壁和沟槽电容器的顶表面上形成离子掺杂区域。 离子掺杂区域被氧化形成氧化物层。 使用氧化物层作为掩模在另一侧壁上形成侧壁半导体层,然后除去氧化物层。 在沟槽的表面上保形地形成阻挡层,并且沟槽填充有导电层。
    • 3. 发明授权
    • Multi-layer hard mask structure for etching deep trench in substrate
    • 用于蚀刻衬底深沟槽的多层硬掩模结构
    • US07029753B2
    • 2006-04-18
    • US10727790
    • 2003-12-04
    • Kaan-Lu TzouTzu-Ching TsaiYi-Nan Chen
    • Kaan-Lu TzouTzu-Ching TsaiYi-Nan Chen
    • B23B17/06
    • H01L27/1087C03C15/00H01L21/0332H01L21/3081
    • A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
    • 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构,其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃(BSG)层和上覆的第一未掺杂硅玻璃(USG)层组成,第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层,然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板,同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。
    • 4. 发明授权
    • Method of forming geometric deep trench capacitors
    • 形成几何深沟槽电容器的方法
    • US06964926B2
    • 2005-11-15
    • US10727924
    • 2003-12-04
    • Tse-Yao HuangYi-Nan ChenTzu-Ching Tsai
    • Tse-Yao HuangYi-Nan ChenTzu-Ching Tsai
    • H01L21/20H01L21/308H01L21/334H01L21/762H01L21/8242H01L27/108
    • H01L27/1087H01L27/10829H01L29/66181Y10S438/942
    • A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.
    • 一种形成具有几何深沟槽的电容器的方法。 首先,提供在其上形成有衬垫结构的衬底,并且在衬垫结构上形成第一硬掩模层。 接着,在第一硬掩模层上形成第二硬掩模层。 接下来,在第一硬掩模层上的第一开口中形成间隔层以露出第二开口。 接下来,在第二开口填充第三硬掩模层,并且移除间隔层。 接下来,第一硬掩模层被蚀刻以暴露具有第一硬掩模层的凸起的第三开口,第二硬掩模层和第三硬掩模层用作掩模。 最后,蚀刻第一硬掩模层,焊盘结构和衬底以形成几何深沟槽。
    • 7. 发明授权
    • Method of fabricating a semiconductor device
    • 制造半导体器件的方法
    • US07807558B2
    • 2010-10-05
    • US11933732
    • 2007-11-01
    • Tzu-Ching TsaiTse-Yao HuangYi-Nan Chen
    • Tzu-Ching TsaiTse-Yao HuangYi-Nan Chen
    • H01L21/3205H01L21/4763
    • H01L21/02063H01L21/02071H01L21/32137
    • A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide.
    • 提供一种制造半导体器件的方法。 制造半导体器件的方法包括提供衬底。 接下来,依次在基板上形成绝缘层,导电层和硅化物层。 接下来,在暴露硅化物层的一部分的硅化物层上形成硬掩模层。 执行第一蚀刻步骤以去除未被硬掩模层覆盖的硅化物层和下面的导电层,从而形成栅极堆叠。 接下来,执行第二蚀刻步骤以在第一蚀刻步骤之后去除未被硬掩模层覆盖的剩余导电层。 用包含氢氧化铵的蚀刻剂进行第二蚀刻步骤。
    • 9. 发明授权
    • Method of filling bit line contact via
    • 填充位线接触的方法
    • US07026207B2
    • 2006-04-11
    • US10715611
    • 2003-11-18
    • Tzu-Ching TsaiYi-Nan Chen
    • Tzu-Ching TsaiYi-Nan Chen
    • H01L21/8238
    • H01L27/10888H01L21/76877H01L27/10894
    • A method of filling a bit line contact via. The method includes providing a substrate having a device region and periphery region, the device region having a transistor, having a gate electrode, drain region, and source region, on the substrate, forming a dielectric layer overlying the substrate, the dielectric layer having a bit line contact via exposing the drain region, and periphery contact via exposing the periphery region, forming a doped conductive layer, lower than the dielectric layer, overlying the drain region, conformally forming a barrier layer overlying the dielectric layer, doped conductive layer, and periphery region, and forming a first conductive layer filling the bit line contact via and periphery contact via.
    • 填充位线接触通孔的方法。 该方法包括提供具有器件区域和外围区域的衬底,器件区域具有在衬底上的栅电极,漏极区和源极区的晶体管,形成覆盖衬底的电介质层,电介质层具有 通过暴露漏极区域和周边接触,通过暴露外围区域形成位线接触,形成覆盖漏极区域的低于介电层的掺杂导电层,保形地形成覆盖在电介质层上的阻挡层,掺杂导电层和 并且形成填充位线接触通孔和周边接触通孔的第一导电层。
    • 10. 发明授权
    • Method of forming inter-metal dielectric
    • 形成金属间电介质的方法
    • US06709975B2
    • 2004-03-23
    • US10222349
    • 2002-08-16
    • Hui Min MaoYi-Nan ChenTzu-Ching Tsai
    • Hui Min MaoYi-Nan ChenTzu-Ching Tsai
    • H01L214763
    • H01L21/76837H01L21/76885
    • A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.
    • 一种形成金属间电介质(IMD)的方法。 其上具有图案化金属层的衬底具有至少一个露出衬底的开口。 开口的长宽比为3.5〜4.5。 接下来,开口填充有第一电介质层,并且由于高纵横比开口,在第一电介质层的上部形成空隙。 此后,蚀刻第一电介质层以使第一介电层在开口中具有预定的高度而没有空隙。 最后,在第一电介质层上形成第二电介质层以完全填充开口。