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31. 发明授权

US06842597B2 Image formation apparatus including an overlap between portions of a photosensitive drum and an adjacent developer unit 失效
标题翻译：图像形成装置包括感光鼓和相邻显影剂单元的部分之间的重叠
公开(公告)号：US06842597B2
公开(公告)日：2005-01-11
申请号：US10376771
申请日：2003-02-28
申请人： Naoki Yamaguchi , Yuzo Kawano , Masakazu Aoki , Hirokazu Tasaka , Yoshihiro Mizoguchi
发明人： Naoki Yamaguchi , Yuzo Kawano , Masakazu Aoki , Hirokazu Tasaka , Yoshihiro Mizoguchi
IPC分类号： G03G15/00 , G03G15/01
CPC分类号： G03G15/0194 , G03G15/0121
摘要： A color image formation apparatus includes a plurality of stages of photosensitive drums provided for respective developing agents, the photosensitive drums arranged in a predetermined direction; and developer units which are provided for respective photosensitive drums and which develop electrostatic latent images formed on the photosensitive drums, wherein an overlap exists in the predetermined direction between a portion of each photosensitive drum and a portion of the developer unit provided so as to correspond to an adjacent photosensitive drum.
摘要翻译：彩色图像形成装置包括为各显影剂设置的多级感光鼓，感光鼓沿预定方向排列; 和显影单元，其被设置用于各个感光鼓并且显影形成在感光鼓上的静电潜像，其中在每个感光鼓的一部分和显影单元的一部分之间的预定方向上存在重叠，相邻的感光鼓。

32. 发明授权

US06461112B1 Screw compression apparatus and operation control method thereof 有权
标题翻译：螺杆压缩装置及其操作控制方法
公开(公告)号：US06461112B1
公开(公告)日：2002-10-08
申请号：US09671305
申请日：2000-09-28
申请人： Hiroshi Ohta , Masakazu Aoki , Hiroyuki Matsuda , Hitoshi Nishimura
发明人： Hiroshi Ohta , Masakazu Aoki , Hiroyuki Matsuda , Hitoshi Nishimura
IPC分类号： F04B4900
CPC分类号： F04C28/08 , F04C18/16 , F04C2240/403 , F04C2270/02 , F04C2270/18
摘要： In a capacity control method for an oil-free screw compressor, when an air consumption is larger than a set amount, a rotation frequency of a motor using an inverter to drive the compressor is set to be variable. When the air consumption is a set air amount or less, the inverter is controlled in such a manner that the rotation frequency of the motor is kept at a constant value. In this state, when an operation gas pressure of the compressor reaches an upper-limit value, an air release valve is opened to discharge the operation gas to the atmosphere. Additionally, the rotation frequency of the motor is lowered to a lower-limit value. Re-compression in the compressor can be prevented, and a compressor drive torque is lowered.
摘要翻译：在无油螺杆压缩机的容量控制方法中，当空气消耗量大于设定量时，使用变频器驱动压缩机的电动机的旋转频率被设定为可变的。当空气消耗量为设定的空气量以下时，以使电机的旋转频率保持恒定的方式来控制逆变器。在该状态下，当压缩机的运转气体压力达到上限值时，打开排气阀，将操作气体排出到大气中。此外，电动机的旋转频率降低到下限值。可以防止压缩机中的再压缩，并且压缩机驱动转矩降低。

33. 发明授权

US06450791B1 Scroll compressor 有权
公开(公告)号：US06450791B1
公开(公告)日：2002-09-17
申请号：US09908843
申请日：2001-07-20
申请人： Natsuki Kawabata , Kazuaki Shiinoki , Masakazu Aoki , Shigeru Machida , Toshiaki Yabe
发明人： Natsuki Kawabata , Kazuaki Shiinoki , Masakazu Aoki , Shigeru Machida , Toshiaki Yabe
IPC分类号： F01C102
CPC分类号： F04C18/0223 , F01C21/08 , F04C18/0253 , F04C18/0284 , F04C29/0092 , F04C29/04
摘要： In a double toothed type scroll compressor, spiral wraps are formed on both sides of an end plate of an orbiting scroll, and wraps adapted to engage with the spiral wraps are formed on a stationary scroll. A dust wrap is formed on a side diametrically outside of the wrap of the stationary scroll. Grooves are formed on ends of the respective wraps to receive therein seal members formed of a high polymer material. Electric charge of static electricity produced when the seal members slide on surfaces of the mating end plate is made to flow from a bolt provided on an end of a crankshaft to the stationary scroll through a brush, thereby preventing accumulation of electric charge in a crankshaft.

34. 发明授权

US06414530B2 Semiconductor integrated circuit device, semiconductor memory system and clock synchronous circuit 失效
标题翻译：半导体集成电路器件，半导体存储器系统和时钟同步电路
公开(公告)号：US06414530B2
公开(公告)日：2002-07-02
申请号：US09832019
申请日：2001-04-11
申请人： Hiromasa Noda , Masakazu Aoki , Hitoshi Tanaka , Hideyuki Aoki
发明人： Hiromasa Noda , Masakazu Aoki , Hitoshi Tanaka , Hideyuki Aoki
IPC分类号： H03K1126
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/22 , G11C7/222 , H03K5/133 , H03K5/135 , H03K5/1504
摘要： A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
摘要翻译：格子状延迟电路被配置为其中分别设置有用于分别耦合输入到第一和第二输入端子的两个输入信号的阻抗元件的多个逻辑门电路，并且分别形成通过将输入到第一和第二输入端的输入信号反相而获得的输出信号和第二信号被使用以在第一信号传送方向和第二信号传送方向上以格子形式布置。输入时钟信号在第一信号传送方向上被连续地延迟，然后输入到从第一信号传输方向看到的从第一到最后的逻辑门电路。输出信号从放置在至少多个级的逻辑门电路的输出端获得，如第二信号传送方向所示，并且被布置在第一信号传送方向。

35. 发明授权

US06396761B2 Semiconductor integrated circuit device and method of activating the same 有权
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US06396761B2
公开(公告)日：2002-05-28
申请号：US09875169
申请日：2001-06-07
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线之间的并行形式提供多个开关MOSFET，其不需要在其非正常状态下的存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

36. 发明授权

US06281711B1 Semiconductor integrated circuit device having power reduction mechanism 有权
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US06281711B1
公开(公告)日：2001-08-28
申请号：US09291977
申请日：1999-04-15
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

37. 发明授权

US5955896A Input buffer using a differential amplifier 失效
标题翻译：使用差分放大器的输入缓冲器
公开(公告)号：US5955896A
公开(公告)日：1999-09-21
申请号：US606852
申请日：1996-02-26
申请人： Masashi Horiguchi , Jun Etoh , Takeshi Sakata , Kan Takeuchi , Katsumi Matsuno , Masakazu Aoki
发明人： Masashi Horiguchi , Jun Etoh , Takeshi Sakata , Kan Takeuchi , Katsumi Matsuno , Masakazu Aoki
IPC分类号： H03K19/0175 , G11C11/407 , G11C11/408 , H03K5/24 , H03K5/20
CPC分类号： H03K5/2481
摘要： In an input circuit for semiconductor devices, such as an address buffer, an arrangement is provided which obviates the timing margin from capture of an input signal to its latching and outputting, thereby increasing the operation speed of the input circuit. The address buffer includes a differential amplifier Ai which receives an input signal Ai and outputs a pair of differential signals A-come-first-served latch circuit detects, latches and outputs one of the paired differential signals that has changed first. Activation/inactivation of the differential amplifier is done by turning on and off an N-channel MOS transistor through a Set signal. When activated, the differential amplifier generates a potential difference between the paired differential signals and, when inactivated, has its paired differential signals go low.
摘要翻译：在诸如地址缓冲器的半导体器件的输入电路中，提供了一种排除了将时序余量从捕获输入信号到其锁存和输出的布置，从而增加了输入电路的操作速度。地址缓冲器包括差分放大器Ai，其接收输入信号Ai并输出一对差分信号A先来先生的锁存电路检测，锁存和输出首先改变的成对差分信号之一。差分放大器的激活/失活是通过设置信号来打开和关闭N沟道MOS晶体管来实现的。当被激活时，差分放大器产生成对的差分信号之间的电位差，当失活时，它的成对差分信号变低。

38. 发明授权

US5724297A Semiconductor integrated circuit device and method of activating the same 失效
公开(公告)号：US5724297A
公开(公告)日：1998-03-03
申请号：US762883
申请日：1996-12-12
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , H03K19/00 , H03K17/16
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

39. 发明授权

US5691952A Semiconductor memory device and memory module using the same 失效
标题翻译：半导体存储器件和使用其的存储器模块
公开(公告)号：US5691952A
公开(公告)日：1997-11-25
申请号：US590608
申请日：1996-01-24
申请人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
发明人： Toshio Sasaki , Kazumasa Yanagisawa , Toshio Sugano , Kiyoshi Inoue , Seiichiro Tsukui , Masakazu Aoki , Shigeru Suzuki , Masashi Horiguchi
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C29/74 , G11C29/808 , G11C29/832
摘要： Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.
摘要翻译：第一半导体存储器件的输入/输出端子，其中存在以存储器单元为单位的故障或缺陷，并且具有冗余存储器垫的第二半导体存储器件的输入/输出端子在安装的基板上彼此连接，从而减轻故障在记忆垫单位。电源基本上被切断供给故障存储器垫。

40. 发明授权

US5528548A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5528548A
公开(公告)日：1996-06-18
申请号：US384962
申请日：1995-02-07
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , G11C7/00
CPC分类号： H03K17/693 , G05F1/465
摘要： A semiconductor memory is provided which includes a voltage converter supplying an internal supply voltage in proportion to the greater one of two reference voltages to a circuit in the semiconductor memory. The voltage converter includes a circuit which is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as a voltage dividing circuit. The memory also includes a word line booster for boosting the internal supply voltage.
摘要翻译：提供一种半导体存储器，其包括电压转换器，其向半导体存储器中的电路提供与两个参考电压中的较大一个成比例的内部电源电压。电压转换器包括电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一电路用于产生对外部供电电压的依赖性大于第一电压的依赖性。电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压电路。该存储器还包括用于升高内部电源电压的字线升压器。

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