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31. 发明授权

US07195976B2 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device 有权
标题翻译：非易失性半导体存储器及其制造方法，以及半导体器件及其制造方法
公开(公告)号：US07195976B2
公开(公告)日：2007-03-27
申请号：US10851350
申请日：2004-05-24
申请人： Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
摘要翻译：一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极，层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

32. 发明授权

US06982468B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06982468B2
公开(公告)日：2006-01-03
申请号：US10942014
申请日：2004-09-16
申请人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Natsuki Yokoyama , Tsuyoshi Yamauchi
发明人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Natsuki Yokoyama , Tsuyoshi Yamauchi
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film
摘要翻译：一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时将氮气引入未被除去的二氧化硅的表面，依次溶解并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

33. 发明申请

US20050272198A1 Method of manufacturing nonvolatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20050272198A1
公开(公告)日：2005-12-08
申请号：US11144593
申请日：2005-06-06
申请人： Hirotaka Hamamura , Toshiyuki Mine , Natsuki Yokoyama
发明人： Hirotaka Hamamura , Toshiyuki Mine , Natsuki Yokoyama
IPC分类号： H01L27/10 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/42344 , H01L29/513 , H01L29/792
摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed. For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.
摘要翻译：通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

34. 发明申请

US20050090058A1 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device 有权
公开(公告)号：US20050090058A1
公开(公告)日：2005-04-28
申请号：US10954102
申请日：2004-09-30
申请人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01M10/0525 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , G11C27/00 , H01L21/00 , H01L21/28 , H01L21/283 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/94 , H01L31/062 , H01L31/119 , H01M2/16
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

35. 发明授权

US06521943B1 Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture 有权
标题翻译：具有与栅绝缘体相邻的薄电极层的半导体器件及其制造方法
公开(公告)号：US06521943B1
公开(公告)日：2003-02-18
申请号：US09520346
申请日：2000-03-07
申请人： Toshiyuki Mine , Jiro Yugami , Takashi Kobayashi , Masahiro Ushiyama
发明人： Toshiyuki Mine , Jiro Yugami , Takashi Kobayashi , Masahiro Ushiyama
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.
摘要翻译：公开了一种半导体器件（例如非易失性半导体存储器件）及其形成方法。该器件包括在栅极绝缘膜上具有非晶硅膜的第一层或多晶硅薄膜或非晶硅和多晶硅的组合的膜的栅电极（例如，浮栅电极）。当膜包括多晶硅时，膜的厚度小于10nm。可以在第一层上或覆盖第一层上提供较厚的多晶硅膜。存储器件可以显着增加写入/擦除电流，而不会在施加应力之后增加低电场漏电流，这反过来大大降低了写入/擦除时间。在形成半导体器件时，可以在栅极绝缘膜上提供薄的非晶或多晶硅膜，以及设置在非晶硅膜上的薄绝缘膜，其上设置有较厚的多晶硅膜或覆盖薄绝缘膜。在薄硅膜是非晶硅的情况下，其然后可以多晶化，尽管不需要。还公开了基于层厚度的非晶硅层的选择性结晶的技术。

36. 发明授权

US06444554B1 Method of making a non-volatile memory and semiconductor device 有权
标题翻译：制造非易失性存储器和半导体器件的方法
公开(公告)号：US06444554B1
公开(公告)日：2002-09-03
申请号：US10011731
申请日：2001-12-11
申请人： Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01L21283
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
摘要翻译：一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极，层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

37. 发明授权

US6144062A Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture 失效
公开(公告)号：US6144062A
公开(公告)日：2000-11-07
申请号：US41793
申请日：1998-03-13
申请人： Toshiyuki Mine , Jiro Yugami , Takashi Kobayashi , Masahiro Ushiyama
发明人： Toshiyuki Mine , Jiro Yugami , Takashi Kobayashi , Masahiro Ushiyama
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7883
摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

38. 发明授权

US5091761A Semiconductor device having an arrangement of IGFETs and capacitors stacked thereover 失效
标题翻译：具有集成在其上的IGFET和电容器的布置的半导体器件
公开(公告)号：US5091761A
公开(公告)日：1992-02-25
申请号：US384821
申请日：1989-07-25
申请人： Atsushi Hiraiwa , Shinichiro Kimura , Toshiyuki Mine , Takashi Kobayashi , Tokuo Kure , Shinpei Iijima , Jiro Yugami
发明人： Atsushi Hiraiwa , Shinichiro Kimura , Toshiyuki Mine , Takashi Kobayashi , Tokuo Kure , Shinpei Iijima , Jiro Yugami
IPC分类号： H01L27/108
CPC分类号： H01L27/10808
摘要： Disclosed is a semiconductor device including a charge storage capacitor having a storage electrode which is electrically connected to a switching transistor through a contact hole provided in an insulator and which has a greater film thickness than the radius of the contact hole, at least a part of the storage electrode being disposed above a data line. It is possible to reduce the memory cell area while preventing lowering in the capacitance, and thus realize high density and high integration of semiconductor devices.
摘要翻译：公开了一种半导体器件，包括具有存储电极的电荷存储电容器，该存储电极通过设置在绝缘体中的接触孔与开关晶体管电连接并且具有比接触孔的半径更大的膜厚度，至少部分所述存储电极设置在数据线的上方。可以在防止电容降低的同时减小存储单元面积，从而实现半导体器件的高密度和高集成度。

39. 发明授权

US09214516B2 Field effect silicon carbide transistor 有权
标题翻译：场效应碳化硅晶体管
公开(公告)号：US09214516B2
公开(公告)日：2015-12-15
申请号：US14240376
申请日：2012-03-30
申请人： Toshiyuki Mine , Yasuhiro Shimamoto , Hirotaka Hamamura
发明人： Toshiyuki Mine , Yasuhiro Shimamoto , Hirotaka Hamamura
IPC分类号： H01L29/16 , H01L21/04 , H01L29/66 , H01L29/78 , H01L29/792
CPC分类号： H01L29/1608 , H01L21/046 , H01L21/049 , H01L29/513 , H01L29/66068 , H01L29/7802 , H01L29/7828 , H01L29/792
摘要： In a SiC-MOSFET power device for which a SiC substrate is used, a laminated insulating film having a charge-trapping characteristic is employed as a gate insulating film of the SiC-DiMOSFET, and charges are injected into the laminated insulating film, thereby suppressing a change in the gate threshold voltage.
摘要翻译：在使用SiC衬底的SiC-MOSFET功率器件中，采用具有电荷俘获特性的层叠绝缘膜作为SiC-DiMOSFET的栅极绝缘膜，并且将电荷注入到层叠绝缘膜中，从而抑制门极电压的变化。

40. 发明申请

US20120316445A1 Ultrasonic transducer and ultrasonic diagnostic device using same 有权
标题翻译：超声波换能器和超声波诊断装置使用相同
公开(公告)号：US20120316445A1
公开(公告)日：2012-12-13
申请号：US13577816
申请日：2011-01-25
申请人： Shuntaro Machida , Taiichi Takezaki , Toshiyuki Mine
发明人： Shuntaro Machida , Taiichi Takezaki , Toshiyuki Mine
IPC分类号： H02N1/08 , A61B8/00
CPC分类号： B06B1/0292 , A61B8/00
摘要： In an ultrasonic transducer comprising a first electrode, a first insulating film disposed on the first electrode, a hollow part provided above the first insulating film and disposed between surfaces above and below the hollow part, a second insulating film disposed above the hollow part, and a second electrode disposed on the second insulating film, a first conductive film disposed on the side of the surface below the hollow part and a second conductive film disposed on the side of the surface above the hollow part are provided, the first conductive film and the second conductive film are disposed so that they overlap with a region in which the surfaces above and below the hollow part contact with each other as seen from above when the transducer is driven, and they do not overlap with each other in the region as seen from above. With such a configuration, there are provided a structure suitable for, even when the surface above the hollow part contacts with the surface below the hollow part, suppressing concentration of electric fields and electric currents in the insulating films in the contact region, and suppressing injection of electrical charge into the insulating films and degradation of dielectric strength thereof, and an ultrasonic diagnostic device using it.
摘要翻译：在包括第一电极的超声换能器中，设置在第一电极上的第一绝缘膜，设置在第一绝缘膜之上并设置在中空部分之上和之下的表面之间的中空部分，设置在中空部分上方的第二绝缘膜，以及设置在第二绝缘膜上的第二电极，设置在中空部分下方的表面侧的第一导电膜和设置在中空部分上方表面侧的第二导电膜，第一导电膜和第二导电膜被设置为使得它们与中空部分的上表面和下表面之间的表面彼此重叠的区域与传感器被驱动时从上方观察到，并且它们在区域中彼此不重叠，如从以上。通过这样的结构，即使当中空部件上方的表面与中空部件下方的表面接触时，也能够抑制接触区域中的绝缘膜中的电场和电流的集中，并抑制注入的绝缘膜中的电荷和介电强度的降低，以及使用它的超声波诊断装置。

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