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1. 发明授权

US06693051B2 Silicon oxide based gate dielectric layer 失效
标题翻译：基于氧化硅的栅介质层
公开(公告)号：US06693051B2
公开(公告)日：2004-02-17
申请号：US09773443
申请日：2001-02-01
申请人： David A Muller , Gregory L. Timp
发明人： David A Muller , Gregory L. Timp
IPC分类号： H01L21283
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L28/56 , H01L29/513 , H01L29/517 , Y10T428/265
摘要： A semiconductor device having a dielectric layer formed between a first and a second conductive layer. The dielectric layer comprising a layer of silicon oxide, SiOX≦2, having a dielectric constant greater than about 3.9 and less than or equal to about 12.
摘要翻译：一种具有形成在第一和第二导电层之间的电介质层的半导体器件。该电介质层包括氧化硅层，SiO 2≤2，介电常数大于约3.9且小于或等于约12。

2. 发明授权

US06358811B1 Method for forming a stoichiometric ferroelectric and/or dielectric thin film layer containing lead or bismuth on an electrode 失效
标题翻译：在电极上形成含有铅或铋的化学计量的铁电和/或电介质薄膜层的方法
公开(公告)号：US06358811B1
公开(公告)日：2002-03-19
申请号：US09275558
申请日：1999-03-24
申请人： Bae Yeon Kim
发明人： Bae Yeon Kim
IPC分类号： H01L21283
CPC分类号： H01L28/56 , H01L21/31691
摘要： An inventive a method for manufacturing a microelectronic structure for use in computer memory applications, sensors, capacitors and various communications applications, the microelectronic structure including a stoichiometric ferroelectric and/or dielectric layer containing lead or bismuth formed on top of an electrode, the method comprising the steps of: forming a lower electrode; forming a self diffusion barrier on top of the lower electrode; heat-treating the self diffusion barrier at a first temperature; forming a ferroelectric and/or dielectric layer on top of the self diffusion barrier; heat-treating the ferroelectric and/or dielectric layer at a second temperature; and forming an upper electrode to thereby form the microelectronic structure, wherein a chemical composition of the self diffusion barrier is the same as that of the ferroelectric and/or dielectric layer after the second heat-treatment. The self diffusion barrier prevents the bismuth or lead component of the ferroelectric and/or dielectric layer from reacting and diffusing to the lower electrode and functions as a perovskite-seed layer for the ferroelectric and/or dielectric layer, making the ferroelectric and/or dielectric layer stoichiometric and lowering the crystallization temperature thereof.
摘要翻译：本发明的一种用于制造用于计算机存储器应用，传感器，电容器和各种通信应用的微电子结构的方法，所述微电子结构包括在电极顶部形成含有铅或铋的化学计量的铁电和/或介电层，所述方法包括步骤：形成下电极; 在下电极的顶部形成自扩散阻挡层; 在第一温度下热处理自扩散阻挡层; 在自扩散阻挡层的顶部形成铁电体和/或电介质层; 在第二温度下对铁电体和/或电介质层进行热处理; 并形成上电极，从而形成微电子结构，其中自扩散阻挡层的化学组成与第二热处理后的铁电体和/或介电层的化学组成相同。自扩散阻挡层阻止铁电体和/或介电层的铋或铅成分与下电极反应并扩散，并用作铁电体和/或电介质层的钙钛矿种子层，从而形成铁电体和/或电介质层化学计量并降低其结晶温度。

3. 发明授权

US06458683B1 Method for forming aluminum bumps by CVD and wet etch 有权
标题翻译：通过CVD和湿蚀刻形成铝凸块的方法
公开(公告)号：US06458683B1
公开(公告)日：2002-10-01
申请号：US09821930
申请日：2001-03-30
申请人： Cheng-Wei Lee
发明人： Cheng-Wei Lee
IPC分类号： H01L21283
CPC分类号： H01L24/11 , H01L21/28562 , H01L2224/13099 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014
摘要： A method for forming aluminum bumps that has significantly reduced processing steps than the conventional method is disclosed. The method utilizes a chemical vapor deposition technique for the selective deposition of aluminum into an opening for forming the bump and then a wet etch process for removing a polyimide layer that functioned both as a photoresist layer for providing an opening in a passivation layer and as a support for a via hole during the selective aluminum deposition process. The thickness of the passivation layer and the polyimide layer formed on top of the metal I/O pad is important since it determines the height of the aluminum bump formed.
摘要翻译：公开了一种形成铝凸块的方法，其具有比常规方法显着减少的加工步骤。该方法利用化学气相沉积技术将铝选择性沉积到用于形成凸块的开口中，然后用于去除用作在钝化层中提供开口的光致抗蚀剂层的聚酰亚胺层的湿蚀刻工艺，以及作为在选择性铝沉积过程中支撑通孔。形成在金属I / O焊盘顶部的钝化层和聚酰亚胺层的厚度是重要的，因为它决定了形成的铝凸块的高度。

4. 发明授权

US06323120B1 Method of forming a wiring film 失效
标题翻译：形成布线膜的方法
公开(公告)号：US06323120B1
公开(公告)日：2001-11-27
申请号：US09522473
申请日：2000-03-09
申请人： Takao Fujikawa , Yutaka Narukawa , Kohei Suzuki , Takuya Masui
发明人： Takao Fujikawa , Yutaka Narukawa , Kohei Suzuki , Takuya Masui
IPC分类号： H01L21283
CPC分类号： H01L21/76873 , H01L21/76843 , H01L21/76882
摘要： A method of forming an intact wiring film by applying a filling treatment with a metal material with no pores to holes/trenches, the method comprising forming a barrier layer 3 to an insulation film 2 having holes/trenches 2A, forming a seed layer by a PVD method on the surface of the barrier layer and laminating a wiring film 5A by a electrolytic plating method and heat treating the same under a high temperature/high pressure gas atmosphere.
摘要翻译：通过对孔/沟槽没有孔的金属材料进行填充处理来形成完整的布线膜的方法，该方法包括在具有孔/沟槽2A的绝缘膜2上形成阻挡层3，形成阻挡层3，通过 PVD法，通过电解电镀法层叠布线膜5A，并在高温高压气体气氛下进行热处理。

5. 发明授权

US06297073B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06297073B1
公开(公告)日：2001-10-02
申请号：US09547937
申请日：2000-04-11
申请人： Makoto Kitano , Ryuji Kohno , Naotaka Tanaka , Akihiro Yaguchi , Tetsuo Kumazawa , Ichiro Anjoh , Hideki Tanaka , Asao Nishimura , Shuji Eguchi , Akira Nagai , Mamoru Mita
发明人： Makoto Kitano , Ryuji Kohno , Naotaka Tanaka , Akihiro Yaguchi , Tetsuo Kumazawa , Ichiro Anjoh , Hideki Tanaka , Asao Nishimura , Shuji Eguchi , Akira Nagai , Mamoru Mita
IPC分类号： H01L21283
CPC分类号： H01L24/50 , H01L23/3114 , H01L23/49572 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01052 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/15787 , H01L2924/00
摘要： A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.
摘要翻译：提供一种半导体器件，具有多个用于外部连接的电极的半导体芯片，除弹性体树脂形成的弹性体树脂部分，其除了多个电极中的至少一些外部结合到半导体芯片，包括树脂的带层，包括表面上的带状布线图案，用于将印刷布线图案接合到带布线图案的多个焊料凸块，用于将半导体芯片的多个电极连接到带布线图案的引线，以及密封用于覆盖引线的树脂，由引线连接的多个电极。弹性体树脂的横向弹性模量不小于50MPa且不大于750MPa。

6. 发明授权

US06774023B1 Method of manufacturing a semiconductor device having a multilayer structure including a dual-layer silicide 失效
标题翻译：制造具有包括双层硅化物的多层结构的半导体器件的方法
公开(公告)号：US06774023B1
公开(公告)日：2004-08-10
申请号：US08068708
申请日：1993-05-28
申请人： Su-Hyon Paek , Jin-Seog Choi
发明人： Su-Hyon Paek , Jin-Seog Choi
IPC分类号： H01L21283
CPC分类号： H01L23/53271 , H01L21/76889 , H01L23/532 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which includes a silicon substrate, an oxide layer formed on the silicon substrate, a polysilicon layer formed on the oxide layer, a first metal silicide layer formed on the polysilicon layer, and a second metal silicide layer formed on the first metal silicide layer, and a method for fabricating the same. The first metal silicide layer is preferably comprised of a metal silicide, such as molybdenum, tungsten, or tantalum silicide, having a melting point which is higher than that of the second metal silicide layer. The second metal silicide layer is preferably comprised of titanium silicide. In an embodiment, the method comprises forming the polysilicon layer on the oxide layer, depositing a tantalum layer on the polysilicon layer, rapidly annealing the resulting structure.
摘要翻译：一种半导体器件，包括硅衬底，形成在硅衬底上的氧化物层，形成在氧化物层上的多晶硅层，形成在多晶硅层上的第一金属硅化物层和形成在第一金属硅化物上的第二金属硅化物层层及其制造方法。第一金属硅化物层优选由金属硅化物，例如钼，钨或硅化钽组成，其熔点高于第二金属硅化物层的熔点。第二金属硅化物层优选由硅化钛构成。在一个实施例中，该方法包括在氧化物层上形成多晶硅层，在多晶硅层上沉积钽层，快速退火所得到的结构。

7. 发明授权

US06576967B1 Semiconductor structure and process for forming a metal oxy-nitride dielectric layer 有权
标题翻译：用于形成金属氧化氮介电层的半导体结构和工艺
公开(公告)号：US06576967B1
公开(公告)日：2003-06-10
申请号：US09663919
申请日：2000-09-18
申请人： James K. Schaeffer, III , Mark V. Raymond , Bich-Yen Nguyen
发明人： James K. Schaeffer, III , Mark V. Raymond , Bich-Yen Nguyen
IPC分类号： H01L21283
CPC分类号： H01L21/28202 , H01L21/28194 , H01L21/3143 , H01L29/518
摘要： The invention relates to a semiconductor device and the process of forming a metal oxy-nitride gate dielectric layer or a metal-silicon oxy-nitride gate dielectric layer. The metal oxy-nitride or metal-silicon oxy-nitride dielectric layer comprises at least one of a metal, silicon, oxygen, and nitrogen atoms where the nitrogen to oxygen atomic ratio is at least 1:2. The metal oxy-nitride or metal-silicon oxy-nitride material has a higher dielectric constant in comparison with a silicon dioxide, providing similar or improved electrical characteristics with a thicker thickness. Other benefits include reduced leakage properties, improved thermal stability, and reduced capacitance versus voltage (CV) hysteresis offset.
摘要翻译：本发明涉及一种半导体器件和形成金属氮氧化物栅介电层或金属硅氧氮化物栅介电层的工艺。金属氮氧化物或金属硅氧氮化物电介质层包括金属，硅，氧和氮原子中的至少一种，其中氮与氧原子比至少为1:2。与二氧化硅相比，金属氧化氮化物或金属硅氧氮化物材料具有更高的介电常数，提供具有较厚厚度的相似或改进的电气特性。其他优点包括降低泄漏特性，改善热稳定性，降低电容对电压（CV）滞后补偿。

8. 发明授权

US06444554B1 Method of making a non-volatile memory and semiconductor device 有权
标题翻译：制造非易失性存储器和半导体器件的方法
公开(公告)号：US06444554B1
公开(公告)日：2002-09-03
申请号：US10011731
申请日：2001-12-11
申请人： Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01L21283
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
摘要翻译：一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极，层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

9. 发明授权

US06566278B1 Method for densification of CVD carbon-doped silicon oxide films through UV irradiation 有权
标题翻译：通过UV照射使CVD碳掺杂氧化硅膜致密化的方法
公开(公告)号：US06566278B1
公开(公告)日：2003-05-20
申请号：US09648289
申请日：2000-08-24
申请人： Keith R. Harvey , Tian-Hoe Lim , Li-Qun Xia
发明人： Keith R. Harvey , Tian-Hoe Lim , Li-Qun Xia
IPC分类号： H01L21283
CPC分类号： H01L21/02126 , C23C16/401 , C23C16/56 , H01L21/02211 , H01L21/02271 , H01L21/02348 , H01L21/31633 , H01L21/76825 , H01L21/76828
摘要： Carbon-doped silicon oxide films (SiCxOy) produced by CVD of an organosilane gas containing at least one silicon carbon bond, are rapidly densified by exposure to ultraviolet radiation. UV radiation exposure disrupts undesirable chemical bonds (such as Si—OH) present in the carbon-doped silicon oxide following deposition, replacing these bonds with more desirable chemical bonds characteristic of an ordered silicon oxide lattice. As a result of radiation exposure and the chemical bond replacement, gases such as water vapor are evolved and removed, producing a densified and stable carbon-doped silicon oxide film. Densification utilizing ultraviolet radiation is particularly useful because softness and fragility of freshly-deposited (SiCxOy) films may preclude insertion and removal of coated substrates from conventional batch loaded thermal annealing chambers.
摘要翻译：通过含有至少一个硅碳键的有机硅烷气体CVD生产的碳掺杂氧化硅膜（SiCxOy）通过暴露于紫外线辐射而迅速致密化。紫外辐射暴露破坏沉积后存在于碳掺杂氧化硅中的不期望的化学键（例如Si-OH），用有序氧化硅晶格特征的更理想的化学键代替这些键。作为辐射暴露和化学键置换的结果，放出并除去诸如水蒸气的气体，产生致密和稳定的碳掺杂氧化硅膜。利用紫外线辐射的致密特别有用，因为新沉积（SiCxOy）膜的柔软性和脆性可能妨碍从常规的批量加载热退火室中插入和除去涂覆的基材。

10. 发明授权

US06486049B2 Method of fabricating semiconductor devices with contact studs formed without major polishing defects 有权
标题翻译：制造具有不具有主要抛光缺陷的接触螺柱的半导体器件的方法
公开(公告)号：US06486049B2
公开(公告)日：2002-11-26
申请号：US09845600
申请日：2001-04-30
申请人： John Maltabes , Hans Zeindl
发明人： John Maltabes , Hans Zeindl
IPC分类号： H01L21283
CPC分类号： H01L21/7684 , H01L21/76819 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a contact stud (100) contacts a semiconductor substrate (10); the stud is embedded in an insulating structure with a first insulating layer (20) and a second insulating layer (20′). During manufacturing, (a) the first layer (20) is provided above the substrate (10); (b) a hole in the first layer (20) exposes a portion of the upper surface of the substrate to receive the stud; (c) a contact material (30, 40) is provided at the top of the resulting structure; (d) a first chemical-mechanical polishing (CMP) removes the contact material from the surface of the first layer (20) outside the hole; (e) residuals (50) of the contact material are cleaned away from the upper surface; (f) the second insulating layer (20′) is provided at the surface of the resulting structure; (g) and further polishing is applied.
摘要翻译：在半导体器件中，接触柱（100）接触半导体衬底（10）; 螺柱嵌入具有第一绝缘层（20）和第二绝缘层（20'）的绝缘结构中。在制造过程中，（a）第一层（20）设置在基板（10）上方; （b）所述第一层（20）中的孔暴露所述基板的上表面的一部分以接收所述螺柱; （c）在所得结构的顶部设置接触材料（30,40）; （d）第一化学机械抛光（CMP）从孔外的第一层（20）的表面去除接触材料; （e）接触材料的残余物（50）从上表面被清除; （f）在所得结构的表面设置第二绝缘层（20'）; （g）并进一步研磨。

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