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31. 发明授权

US5453952A Semiconductor device having peripheral circuit formed of TFT (thin film transistor) 失效
标题翻译：具有由TFT（薄膜晶体管）形成的外围电路的半导体装置
公开(公告)号：US5453952A
公开(公告)日：1995-09-26
申请号：US869937
申请日：1992-04-17
申请人： Tomonori Okudaira , Kaoru Motonami
发明人： Tomonori Okudaira , Kaoru Motonami
IPC分类号： G11C11/401 , H01L21/768 , H01L21/822 , H01L27/00 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/12 , H01L29/78
CPC分类号： H01L27/1203 , H01L27/0688 , H01L27/0922 , H01L27/105 , H01L27/10808
摘要： A semiconductor device having an increased integration density. The semiconductor device includes a memory cell array, and a peripheral circuit region formed over the memory cell array and to be in electrical connection to the memory cell array for controlling the input/output of the data signals. A large part of a semiconductor chip area can therefore be used for the memory cell array, thereby increasing the integration density of the semiconductor device.
摘要翻译：具有增加的集成密度的半导体器件。半导体器件包括存储单元阵列和形成在存储单元阵列上并与存储单元阵列电连接的外围电路区域，用于控制数据信号的输入/输出。因此，可以将半导体芯片面积的大部分用于存储单元阵列，从而提高半导体器件的集成密度。

32. 发明授权

US5441916A Method of manufacturing semiconductor device comprising interconnection 失效
标题翻译：制造包括互连的半导体器件的方法
公开(公告)号：US5441916A
公开(公告)日：1995-08-15
申请号：US234806
申请日：1994-04-28
申请人： Kaoru Motonami
发明人： Kaoru Motonami
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417 , H01L21/283 , H01L21/312
CPC分类号： H01L27/10852 , H01L27/10808 , Y10S438/926
摘要： In a semiconductor device, a first conductive interconnection layer and a second conductive interconnection layer are formed respectively on a lower surface and a higher surface of an interlayer insulation film interposing a step-like portion therebetween by employing different photolithography and etching. A dummy interconnection is provided directly beneath the second conductive interconnection layer in the vicinity of the step-like portion. The first and second conductive interconnection layers and are electrically connected to each other by a conductive layer formed directly on the dummy interconnection in a region including the step-like portion to extend over the surface of a silicon substrate. Consequently, even if the step-like portion is larger than depth of focus, the first and second conductive interconnection layers are precisely patterned within depth of focus.
摘要翻译：在半导体器件中，通过使用不同的光刻和蚀刻，分别在夹层间绝缘膜的下表面和更高表面上形成第一导电互连层和第二导电互连层。在阶梯状部分附近的第二导电互连层的正下方设有虚设互连。第一和第二导电互连层并且通过在包括阶梯状部分的区域中直接形成在虚设互连上的导电层彼此电连接以在硅衬底的表面上延伸。因此，即使阶梯状部分大于聚焦深度，第一和第二导电互连层在焦深的范围内被精确地图案化。

33. 发明授权

US5241212A Semiconductor device having a redundant circuit portion and a manufacturing method of the same 失效
标题翻译：具有冗余电路部分的半导体器件及其制造方法
公开(公告)号：US5241212A
公开(公告)日：1993-08-31
申请号：US994436
申请日：1992-12-21
申请人： Kaoru Motonami , Masao Nagatomo
发明人： Kaoru Motonami , Masao Nagatomo
IPC分类号： H01L21/66 , H01L23/525 , H01L23/528
CPC分类号： H01L22/22 , H01L23/5258 , H01L23/5283 , H01L2924/0002
摘要： A semiconductor device includes a specific circuit portion having a predetermined function and a spare redundant circuit portion having the same function as the specific circuit portion. The semiconductor device includes a silicon substrate (1), an interlayer insulating film (2), an LT fuse (3), interconnection layers (4), a testing electrode (5) and a protection film (6). The interlayer insulating film (2) has a groove (11) and is formed on the silicon substrate (1). The LT fuse (3) is formed of polysilicon and is located immediately below the bottom wall of the groove (11). The interconnection layers (4) are formed on the interlayer insulating film (2) with the groove (11) therebetween. The testing electrode (5) is spaced from the interconnection layers (4) and is formed on the interlayer insulating film (2). The protection film (6) is formed on the interlayer insulating film to cover surfaces of the interconnection layers (4) and expose a surface of the testing electrode (5). A laser beam is irradiated to a bottom wall of the groove (11) to fuse and remove a part of the LT fuse (3). This substitutes the specific part having a defect with the redundant circuit portion. In this operation, neither the interconnection layers (4) is damaged, nor short-circuit and breakage thereof are caused.
摘要翻译：半导体器件包括具有预定功能的特定电路部分和具有与特定电路部分相同功能的备用冗余电路部分。半导体器件包括硅衬底（1），层间绝缘膜（2），LT熔丝（3），互连层（4），测试电极（5）和保护膜（6）。层间绝缘膜（2）具有凹槽（11）并形成在硅衬底（1）上。 LT熔丝（3）由多晶硅形成，并且位于槽（11）的底壁的正下方。互连层（4）形成在层间绝缘膜（2）上，其间具有槽（11）。测试电极（5）与互连层（4）间隔开，并形成在层间绝缘膜（2）上。保护膜（6）形成在层间绝缘膜上以覆盖互连层（4）的表面并暴露测试电极（5）的表面。激光束照射到凹槽（11）的底壁，以熔化和去除LT熔丝（3）的一部分。这用具有冗余电路部分的具有缺陷的特定部分代替。在这种操作中，互连层（4）都不会损坏，也不会导致短路和断线。

34. 发明授权

US5157469A Field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulators 失效
标题翻译：具有锥形绝缘子的多层互连层的场效应晶体管
公开(公告)号：US5157469A
公开(公告)日：1992-10-20
申请号：US685398
申请日：1991-04-16
申请人： Tomonori Okudaira , Hideaki Arima , Makoto Ohi , Kaoru Motonami , Yasushi Matsui
发明人： Tomonori Okudaira , Hideaki Arima , Makoto Ohi , Kaoru Motonami , Yasushi Matsui
IPC分类号： H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417 , H01L29/78
CPC分类号： H01L29/41775 , H01L27/10817 , H01L29/7831 , Y10S257/90
摘要： A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.
摘要翻译：公开了一种场效应晶体管及其制造方法，即使在缩小到更高的集成度时，也不会降低多层互连层之间的耐电压特性。该场效应晶体管包括形成在位线15两侧的侧壁21a，使得底侧端接触栅电极4b和4c的侧壁20a的上表面。插入在栅电极4b和4c之间的绝缘膜的厚度和形成电容器的低电极11的基部11a的厚度不降低。即使缩放到更高的集成度，耐压电压的特性也不会在多层互连层之间劣化。

35. 发明授权

US09431479B2 High breakdown voltage semiconductor device having a resurf layer 有权
标题翻译：具有复层的高耐压电压半导体器件
公开(公告)号：US09431479B2
公开(公告)日：2016-08-30
申请号：US12845176
申请日：2010-07-28
申请人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
发明人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
IPC分类号： H01L29/06 , H01L29/40 , H01L29/66 , H01L29/861 , H01L29/16 , H01L29/20 , H01L29/78
CPC分类号： H01L29/0615 , H01L29/063 , H01L29/0638 , H01L29/0657 , H01L29/0661 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/66128 , H01L29/7811 , H01L29/8611
摘要： In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.
摘要翻译：在根据本发明的半导体器件中，在半导体衬底的表面上形成电极层和凹部。此外，在半导体基板中，形成与凹部的底面接触的RESURF层和电极层。此外，在半导体衬底的上表面上形成绝缘膜以便填充凹部。此外，在凹部上方的绝缘膜上形成场板电极。

36. 发明申请

US20110089487A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110089487A1
公开(公告)日：2011-04-21
申请号：US12836922
申请日：2010-07-15
申请人： Kazunari NAKATA , Atsushi Narazaki , Shigeto Honda , Kaoru Motonami
发明人： Kazunari NAKATA , Atsushi Narazaki , Shigeto Honda , Kaoru Motonami
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a strip shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 μm or more.
摘要翻译：半导体器件包括具有第一导电类型的基极层，形成在基极层上并具有第二导电类型的源极层，以及形成在源极层上的绝缘膜。半导体器件还包括穿透基底层的多个栅极结构，以及穿透绝缘膜和源极层并将源极层和基极层彼此电连接的多个导电部件。栅极结构在平面图中形成为带状。导电部分连接到基底层的部分在平面图中形成为条形，并且形成在栅极结构之间。此外，栅极结构和导电部之间的源极层和基极层彼此接触的部分的尺寸为0.36μm以上。

37. 发明申请

US20110084354A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110084354A1
公开(公告)日：2011-04-14
申请号：US12845176
申请日：2010-07-28
申请人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
发明人： Shigeto Honda , Atsushi Narazaki , Kaoru Motonami
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/0615 , H01L29/063 , H01L29/0638 , H01L29/0657 , H01L29/0661 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/66128 , H01L29/7811 , H01L29/8611
摘要： In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.
摘要翻译：在根据本发明的半导体器件中，在半导体衬底的表面上形成电极层和凹部。此外，在半导体基板中，形成与凹部的底面接触的RESURF层和电极层。此外，在半导体衬底的上表面上形成绝缘膜以便填充凹部。此外，在凹部上方的绝缘膜上形成场板电极。

38. 发明申请

US20050045880A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050045880A1
公开(公告)日：2005-03-03
申请号：US10898360
申请日：2004-07-26
申请人： Yasuyoshi Itoh , Kaoru Motonami
发明人： Yasuyoshi Itoh , Kaoru Motonami
IPC分类号： H01L27/04 , H01L21/20 , H01L21/322 , H01L21/336 , H01L21/822 , H01L29/786 , H01L29/04
CPC分类号： H01L29/66757 , H01L29/66765 , H01L29/78675 , H01L29/78678 , Y10S257/913
摘要： A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.
摘要翻译：半导体器件包括用作具有绝缘表面的基板的玻璃基板和位于与该玻璃基板重叠的位置的硅层。硅层包括无定形吸气区域。优选地，硅层包括用作有源元件区域的主区域，并且除了主区域之外的硅层的剩余部分中优选包含吸杂区域。优选地，硅层可以包括用作薄膜晶体管的有源区的部分。

39. 发明授权

US6162674A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6162674A
公开(公告)日：2000-12-19
申请号：US357916
申请日：1999-07-21
申请人： Kaoru Motonami
发明人： Kaoru Motonami
IPC分类号： H01L21/8234 , H01L21/82 , H01L21/8239 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/105
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/1052
摘要： A semiconductor device having a memory device and a logic device formed together on a single chip is provided. A first element region and a second element region of a semiconductor substrate are formed spaced apart from each other with an isolation region therebetween. A floating conductive film is provided on the isolation region.
摘要翻译：提供了具有在单个芯片上一起形成的存储器件和逻辑器件的半导体器件。半导体衬底的第一元件区域和第二元件区域之间具有隔离区域形成为彼此间隔开。在隔离区域上设置浮置导电膜。

40. 发明授权

US6040614A Semiconductor integrated circuit including a capacitor and a fuse element 失效
标题翻译：包括电容器和熔丝元件的半导体集成电路
公开(公告)号：US6040614A
公开(公告)日：2000-03-21
申请号：US33611
申请日：1998-03-03
申请人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
发明人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/105 , H01L27/108 , H01L29/40
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/108 , H01L2924/0002
摘要： A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.
摘要翻译：半导体集成电路包括位于绝缘层上的熔丝元件。绝缘层的表面基本上是光滑的。绝缘层位于电容器的上方。接线位于绝缘层上。熔丝元件和布线包括相同的材料。

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