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    • 33. 发明授权
    • Semiconductor storage apparatus
    • 半导体存储装置
    • US07506099B2
    • 2009-03-17
    • US11519221
    • 2006-09-12
    • Shunichi IwanariYasushi GohouYoshihisa Kato
    • Shunichi IwanariYasushi GohouYoshihisa Kato
    • G06F12/00
    • G06F12/123G06F2212/2022
    • A semiconductor storage apparatus comprising: a ferroelectric memory; an SRAM 30; a counter 41; a CAM 10 that judges whether or not a block of data requested to be read out from the ferroelectric memory is stored in the SRAM 30; a storage control unit 51 that, if a result of the judgment is negative, performs a control to read out the requested block of data from the ferroelectric memory and stores a copy of the read-out block of data into a unit storage area in the SRAM 30 that corresponds to the count value indicated by the counter 41; and a counter control unit 52 that causes the counter 41 to update the count value each time a result of the judgment is negative.
    • 一种半导体存储装置,包括:铁电存储器; 一个SRAM 30; 柜台41 判断从铁电存储器请求读出的数据块是否存储在SRAM30中的CAM10; 存储控制单元51,如果判断结果为否定,则执行控制以从强电介质存储器读出所请求的数据块,并将读出的数据块的副本存储在该单元存储区域中 对应于由计数器41指示的计数值的SRAM 30; 以及计数器控制单元52,每当判断结果为负时,使计数器41更新计数值。
    • 38. 发明授权
    • Semiconductor memory device and drive method therefor
    • 半导体存储器件及其驱动方法
    • US06707704B2
    • 2004-03-16
    • US10392843
    • 2003-03-21
    • Yoshihisa KatoYasuhiro ShimadaTakayoshi Yamada
    • Yoshihisa KatoYasuhiro ShimadaTakayoshi Yamada
    • G11C1122
    • G11C11/22
    • The semiconductor memory device of the invention includes at least three memory cell blocks arranged in a word line direction. Each of the memory cell blocks includes a plurality of memory cells arranged in a bit line direction. Each of the memory cells includes a ferroelectric capacitor for storing data by displacement of polarization of a ferroelectric film and a selection transistor connected to one of paired electrodes of the ferroelectric capacitor. Each of the memory cell blocks also includes: a bit line, a sub-bit line and a source line extending in the bit line direction; and a read transistor having a gate connected to one end of the sub-bit line, a source connected to the source line, and a drain connected to one end of the bit line. The read transistor reads data by detecting the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of a data read memory cell from which data is read among the plurality of memory cells. The sub-bit lines of any two of the memory cell blocks are connected to each other via a sub-bit line coupling switch.
    • 本发明的半导体存储器件包括沿字线方向布置的至少三个存储单元块。 每个存储单元块包括以位线方向排列的多个存储单元。 每个存储单元包括用于通过铁电薄膜的极化位移存储数据的铁电电容器和连接到铁电体电容器的一对电极之一的选择晶体管。 每个存储单元块还包括:位线,子位线和沿位线方向延伸的源极线; 以及读取晶体管,其具有连接到子位线的一端的栅极,连接到源极线的源极和连接到位线的一端的漏极。 读取晶体管通过检测在多个存储单元中从其读取数据的数据读取存储单元的铁电电容器的铁电体的极化的位移来读取数据。 任何两个存储单元块的子位线通过子位线耦合开关相互连接。