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31. 发明申请

US20060080642A1 Program processing apparatus 审中-公开
标题翻译：程序处理装置
公开(公告)号：US20060080642A1
公开(公告)日：2006-04-13
申请号：US11232975
申请日：2005-09-23
申请人： Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi
发明人： Hajime Ogawa , Toshiyuki Sakata , Taketo Heishi
IPC分类号： G06F9/44
CPC分类号： G06F8/443 , G06F8/423
摘要： A program processing apparatus, which can check hint information as represented by a pragma so that a compiler may not create a wrong machine-language program, includes: a syntax analysis unit which analyzes a syntax of a program that includes hint information given by a user to the compiler, for generating analysis information; and an error check unit that checks whether or not the hint information in the program is logically contradictory.
摘要翻译：一种程序处理装置，其可以检查由编译指示表示的提示信息，使得编译器可能不创建错误的机器语言程序，包括：语法分析单元，其分析包括由用户给出的提示信息的程序的语法编译器，用于生成分析信息; 以及检查程序中的提示信息是否逻辑上相矛盾的错误检查单元。

32. 发明申请

US20060031661A1 Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor 有权
标题翻译：读取用于以与wihcih指令中的单元无关的单元执行指令的处理器，以及用于这种处理器的编译器，优化装置，汇编器，链接器，调试器和反汇编器
公开(公告)号：US20060031661A1
公开(公告)日：2006-02-09
申请号：US11245357
申请日：2005-10-07
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/40
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

33. 发明授权

US06904135B2 Compound device and telephone station device connected to the same, and power supply system and portable telephone system using compound device 失效
标题翻译：复合设备和电话站设备连接在一起，电源系统和便携式电话系统使用复合设备
公开(公告)号：US06904135B2
公开(公告)日：2005-06-07
申请号：US10172216
申请日：2002-06-14
申请人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
发明人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
IPC分类号： H04B1/38 , H04B7/26 , H04M1/00 , H04M1/723 , H04M1/725 , H04N5/44 , H04W4/24 , H04W76/02 , H04W88/02 , H04W88/08 , H04W88/14 , H04M11/00 , H04B1/00
CPC分类号： H04B1/005 , H04B1/3805 , H04M1/725 , H04N5/4401 , H04N21/2408 , H04N21/2543 , H04N21/4126 , H04N21/4263 , H04N21/42676 , H04N21/433 , H04N21/43637 , H04N21/44227 , H04N21/443 , H04N21/6112 , H04N21/6162 , H04N21/6168 , H04N21/654 , H04N21/6582 , H04N21/6583
摘要： A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.
摘要翻译：复合设备具有数字电视的结构硬件，连接到天线和电话台，并且通过读取和运行数字电视（DTV）程序或使用通用处理器的基站程序，它具有数字电视的功能和便携式电话基站的功能。复合设备的所有者根据通信记录部分中的记录，收到其订阅的电话费或其电费的折扣。因此，提供了数字电视机被赋予便携式电话基站的功能的复合装置，从而可以实现基站的不足之处，不需要设备投资支出和便携式设备所有者的新颖的基础设施给予经济利益，允许公共使用私人拥有作为便携式电话基站。

34. 发明授权

US08418157B2 Compiler apparatus with flexible optimization 有权
标题翻译：具有灵活优化的编译器
公开(公告)号：US08418157B2
公开(公告)日：2013-04-09
申请号：US12706329
申请日：2010-02-16
申请人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
发明人： Hajime Ogawa , Taketo Heishi , Toshiyuki Sakata , Shuichi Takayama , Shohei Michimoto , Tomoo Hamada , Ryoko Miyachi
IPC分类号： G06F9/45
CPC分类号： G06F8/443
摘要： A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.
摘要翻译：编译器包括检测用户到编译器的指令（选项和编译指示）的分析单元，由处理单元（全局区域分配单元，软件流水线单元，循环展开单元，如果转换单元和配对指令生成单元）执行来自用户的选项和编译指示的单独优化处理，遵循来自分析单元的指令等。全局区域分配单元执行优化处理，在指定要分配给全局区域的变量的最大数据大小，要分配给全局区域的变量的指定，以及关于在全局区域中未分配的变量的指定的选项和编译指示。

35. 发明授权

US08151254B2 Compiler, compiler apparatus and compilation method 有权
标题翻译：编译器，编译器和编译方法
公开(公告)号：US08151254B2
公开(公告)日：2012-04-03
申请号：US11790215
申请日：2007-04-24
申请人： Taketo Heishi , Toshiyuki Sakata , Hajime Ogawa , Ryoko Miyachi , Shuji Miyasaka , Tomokazu Ishikawa
发明人： Taketo Heishi , Toshiyuki Sakata , Hajime Ogawa , Ryoko Miyachi , Shuji Miyasaka , Tomokazu Ishikawa
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/425 , G06F8/427 , G06F8/4441
摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.
摘要翻译：提供包括在源程序101中的操作者定义文件102等以及将源程序101转换为机器语言程序105的编译器100。操作者定义文件102包括通过类定义的各种定点类型操作符的定义。编译器100可以生成有效的高级特定指令，处理器执行并通过扩展功能等进行改进，而不会重复频繁升级编译器本身的版本。编译器100由生成中间代码的中间代码生成单元121构成，机器语言指令替换单元122，其使用机器语言指令代替参考由操作者定义文件102定义的类别的中间代码和优化单元130，执行针对包括替代机器语言指令的中间代码的优化。

36. 发明授权

US07689976B2 Compiler apparatus and linker apparatus 有权
标题翻译：编译器装置和连接器装置
公开(公告)号：US07689976B2
公开(公告)日：2010-03-30
申请号：US10950397
申请日：2004-09-28
申请人： Yasuhiro Yamamoto , Hajime Ogawa , Taketo Heishi , Shohei Michimoto
发明人： Yasuhiro Yamamoto , Hajime Ogawa , Taketo Heishi , Shohei Michimoto
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/4442
摘要： A compiler capable of increasing the hit rate of the cache memory is provided that targets a computer having a cache memory, and that converts a source program into an object program. The compiler causes a computer to analyze group information that is used for grouping data objects included in the source program, and places the data objects into groups based on a result of the analysis. The compiler also causes the computer to generate an object program based on a result of the grouping, where the object program does not allow data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.
摘要翻译：提供了能够提高高速缓冲存储器的命中率的编译器，其目标是具有高速缓冲存储器的计算机，并且将源程序转换为对象程序。编译器使计算机分析用于对源程序中包含的数据对象进行分组的组信息，并根据分析结果将数据对象放入组中。编译器还使得计算机基于分组的结果生成对象程序，其中对象程序不允许属于不同组的数据对象被布置在高速缓冲存储器上具有相同设定编号的任何块中。

37. 发明申请

US20080046690A1 Processor executing SIMD instructions 审中-公开
公开(公告)号：US20080046690A1
公开(公告)日：2008-02-21
申请号：US11896370
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

38. 发明申请

US20070256065A1 Compiler, compiler apparatus and compilation method 有权
公开(公告)号：US20070256065A1
公开(公告)日：2007-11-01
申请号：US11790215
申请日：2007-04-24
申请人： Taketo Heishi , Toshiyuki Sakata , Hajime Ogawa , Ryoko Miyachi , Shuji Miyasaka , Tomokazu Ishikawa
发明人： Taketo Heishi , Toshiyuki Sakata , Hajime Ogawa , Ryoko Miyachi , Shuji Miyasaka , Tomokazu Ishikawa
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/425 , G06F8/427 , G06F8/4441
摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

39. 发明授权

US07237229B2 Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration 有权
标题翻译：调试辅助与源列表的多个迭代并行执行显示对应于每个迭代
公开(公告)号：US07237229B2
公开(公告)日：2007-06-26
申请号：US10287231
申请日：2002-11-04
申请人： Hajime Ogawa , Kiyohiko Sumida , Shuichi Takayama , Katsuhiro Okuno , Taketo Heishi
发明人： Hajime Ogawa , Kiyohiko Sumida , Shuichi Takayama , Katsuhiro Okuno , Taketo Heishi
IPC分类号： G06F9/44
CPC分类号： G06F11/3664 , G06F11/3624
摘要： This invention makes debugging more efficient when an object program is intended for processing a loop made up of n groups of iteration-forming instructions. Instructions in the secondary assembler program each has a combination of a line number “;lx” and an iteration identifier “;ix” attached thereto. The line number “;lx” specifies a source code from which the instruction is generated, and the iteration identifier “;ix” specifies an iteration to which the instruction belongs. When the user sets a breakpoint at an instruction, displayed in the windows are (a) a source code for generating the instruction at the breakpoint and (b) another source code for generating another instruction that belongs to a different group of iteration-forming instructions than the breakpoint instruction.
摘要翻译：当目标程序用于处理由n组迭代形成指令组成的循环时，本发明使调试更有效。辅助汇编程序中的指令各自具有行号“; lx”和附加到其上的迭代标识符“ix”的组合。行号“; lx”指定生成指令的源代码，迭代标识符“ix”指定该指令所属的迭代。当用户在指令处设置断点时，窗口中显示的是（a）用于在断点处生成指令的源代码，（b）用于产生属于不同组迭代形成指令的另一指令的另一源代码比断点指令。

40. 发明授权

US07185176B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07185176B2
公开(公告)日：2007-02-27
申请号：US10449788
申请日：2003-06-02
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Yoshihiro Koga , Manabu Kuroda , Masato Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Shuji Miyasaka
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Yoshihiro Koga , Manabu Kuroda , Masato Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Shuji Miyasaka
IPC分类号： G06F15/80
CPC分类号： G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3885 , G06F9/3887 , G06F15/8015
摘要： A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.
摘要翻译：根据本发明的处理器包括解码单元，操作单元等。当解码单元解码指令“vxaddh Rc，Ra，Rb”时，算术和逻辑/比较运算单元等（i）将寄存器Ra的高16位加到寄存器Rb的低16位，导致寄存器Rc的高16位，与此并行地，（ii）将寄存器Ra的低16位加到寄存器Rb的较高16位，并将结果存储在寄存器Rc的低16位中注册Rc。

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