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31. 发明授权

US08580606B2 Method of forming resistance variable memory device 有权
标题翻译：形成电阻变量存储器件的方法
公开(公告)号：US08580606B2
公开(公告)日：2013-11-12
申请号：US13241315
申请日：2011-09-23
申请人： Jeong-Hee Park , Jung-Hwan Park , Hideki Horii , Sung-Lae Cho
发明人： Jeong-Hee Park , Jung-Hwan Park , Hideki Horii , Sung-Lae Cho
IPC分类号： H01L21/06
CPC分类号： H01L45/1625 , H01L27/2409 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of forming a resistance variable memory device, the method including forming a diode on a semiconductor substrate; forming a lower electrode on the diode; forming a first insulating film on the lower electrode, the first insulating film having an opening; forming a resistance variable film filling the opening such that the resistance variable film includes an amorphous region adjacent to a sidewall of the opening and a crystalline region adjacent to the lower electrode; and forming an upper electrode on the resistance variable film.
摘要翻译：一种形成电阻可变存储器件的方法，所述方法包括在半导体衬底上形成二极管; 在二极管上形成下电极; 在所述下电极上形成第一绝缘膜，所述第一绝缘膜具有开口; 形成填充所述开口的电阻变化膜，使得所述电阻变化膜包括与所述开口的侧壁相邻的非晶区域和与所述下部电极相邻的结晶区域; 并在电阻变化膜上形成上电极。

32. 发明授权

US08507353B2 Method of forming semiconductor device having self-aligned plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US08507353B2
公开(公告)日：2013-08-13
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L21/20 , H01L21/8244
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

33. 发明申请

US20120319069A1 Phase Change Memory Device 审中-公开
标题翻译：相变存储器件
公开(公告)号：US20120319069A1
公开(公告)日：2012-12-20
申请号：US13584011
申请日：2012-08-13
申请人： Young-Lim Park , Sung-Lae Cho , Byoung-Jae Bae , Jin-Il Lee , Hye-Young Park
发明人： Young-Lim Park , Sung-Lae Cho , Byoung-Jae Bae , Jin-Il Lee , Hye-Young Park
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , C23C16/34 , C23C16/45536 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/143 , H01L45/1616 , H01L45/1683
摘要： Provided are a phase change memory device and a method for forming the phase change memory device. The method includes forming a phase change material layer by providing reactive radicals to a substrate. The reactive radicals may comprise precursors for a phase change material and nitrogen.
摘要翻译：提供了一种相变存储器件和形成相变存储器件的方法。该方法包括通过向基底提供反应性基团来形成相变材料层。反应性基团可以包括相变材料和氮的前体。

34. 发明授权

US08034683B2 Method of forming a phase change material layer, method of forming a phase change memory device using the same, and a phase change memory device so formed 有权
标题翻译：形成相变材料层的方法，使用其形成相变存储器件的方法，以及如此形成的相变存储器件
公开(公告)号：US08034683B2
公开(公告)日：2011-10-11
申请号：US11785807
申请日：2007-04-20
申请人： Sung-Lae Cho , Choong-Man Lee , Jin-Il Lee , Sang-Wook Lim , Hye-Young Park , Young-Lim Park
发明人： Sung-Lae Cho , Choong-Man Lee , Jin-Il Lee , Sang-Wook Lim , Hye-Young Park , Young-Lim Park
IPC分类号： H01L21/44
CPC分类号： H01L45/1233 , C23C16/305 , C23C16/45523 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A method of forming a phase change material layer includes preparing a substrate having an insulator and a conductor, loading the substrate into a process housing, injecting a deposition gas into the process housing to selectively form a phase change material layer on an exposed surface of the conductor, and unloading the substrate from the process housing, wherein a lifetime of the deposition gas in the process housing is shorter than a time the deposition gas takes to react by thermal energy.
摘要翻译：形成相变材料层的方法包括制备具有绝缘体和导体的衬底，将衬底装载到工艺外壳中，将沉积气体注入工艺外壳中，以选择性地在所述工艺外壳的暴露表面上形成相变材料层导体，以及从工艺外壳卸载衬底，其中工艺外壳中的沉积气体的寿命短于沉积气体通过热能反应的时间。

35. 发明授权

US08026543B2 Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same 有权
标题翻译：具有相变存储单元的半导体器件，使用该半导体器件的电子系统及其制造方法
公开(公告)号：US08026543B2
公开(公告)日：2011-09-27
申请号：US12338814
申请日：2008-12-18
申请人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
发明人： Yoon-Jong Song , Young-Nam Hwang , Sang-Don Nam , Sung-Lae Cho , Gwan-Hyeob Koh , Choong-Man Lee , Bong-Jin Kuh , Yong-Ho Ha , Su-Youn Lee , Chang-Wook Jeong , Ji-Hye Yi , Kyung-Chang Ryoo , Se-Ho Lee , Su-Jin Ahn , Soon-Oh Park , Jang-Eun Lee
IPC分类号： H01L27/108 , H01L47/00
CPC分类号： H01L29/7843 , H01L27/2436 , H01L29/665 , H01L29/7833 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1666 , H01L45/1675
摘要： A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.
摘要翻译：相变存储器件具有氧化阻挡层以防止存储器细胞污染或氧化。在一个实施例中，半导体存储器件包括设置在半导体衬底上的成型层，相变材料图案和电绝缘材料的氧化屏障。成型层在其上部具有突出部。可相变材料图案的一部分覆盖模制层的突起，并且相变材料图案的另一部分延伸穿过突出部。氧化屏障的电绝缘材料可以覆盖相变材料图案和/或延伸并且覆盖模制层的突起和设置在突起上的相变材料图案的部分邻接的整个区域。

36. 发明申请

US20110032753A1 MEMORY CELLS INCLUDING RESISTANCE VARIABLE MATERIAL PATTERNS OF DIFFERENT COMPOSITIONS 有权
标题翻译：包含不同成分的电阻变化材料的记忆细胞
公开(公告)号：US20110032753A1
公开(公告)日：2011-02-10
申请号：US12853329
申请日：2010-08-10
申请人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
发明人： Hyeong-Geun An , Ik-Soo Kim , Hee-Ju Shin , Dong-Hyun Im , Sung-Lae Cho , Eun-Hee Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2213/56 , G11C2213/72 , H01L27/101
摘要： A non-volatile memory device includes a plurality of word lines, a plurality of bit lines, and an array of variable resistance memory cells each electrically connected between a respective word line and a respective bit line. Each of the memory cells includes first and second resistance variable patterns electrically connected in series between first and second electrodes. A material composition of the first resistance variable pattern is different than a material composition of the second resistance variable pattern. Multi-bit data states of each memory cell are defined by a contiguous increase in size of a programmable high-resistance volume within the first and second resistance variable patterns.
摘要翻译：非易失性存储器件包括多个字线，多个位线，以及每个电连接在相应字线和相应位线之间的可变电阻存储单元阵列。每个存储单元包括在第一和第二电极之间串联电连接的第一和第二电阻可变图案。第一电阻可变图案的材料组成不同于第二电阻变化图案的材料组成。每个存储器单元的多位数据状态由第一和第二电阻变化模式内的可编程高电阻体积的连续增加来定义。

37. 发明申请

US20100248460A1 Method of forming information storage pattern 审中-公开
标题翻译：形成信息存储模式的方法
公开(公告)号：US20100248460A1
公开(公告)日：2010-09-30
申请号：US12659959
申请日：2010-03-26
申请人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Jung-Hyeon Kim
发明人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Jung-Hyeon Kim
IPC分类号： H01L21/365 , H01L21/469 , H01L21/443 , H01L21/465
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A method of forming an information storage pattern, includes placing a semiconductor substrate in a process chamber, injecting first, second and third process gases into the process chamber during a first process to form a lower layer on the substrate based on a first injection time and/or a first pause time, injecting the second process gas into the process chamber during a second process, wherein the second process gas is injected into the process chamber during a first elimination time, injecting a fourth process gas together with the second and third process gases into the process chamber during a third process in accordance with a second injection time and/or a second pause time to form an upper layer on the lower layer, and injecting the second process gas into the process chamber during a fourth process, wherein the second process gas is injected into the process chamber during a second elimination.
摘要翻译：一种形成信息存储图案的方法，包括将半导体衬底放置在处理室中，在第一过程中将第一，第二和第三处理气体注入到处理室中，以在第一注入时间基底上形成下层;以及 /或第一暂停时间，在第二过程期间将第二处理气体注入处理室，其中第二处理气体在第一消除时间期间被注入到处理室中，与第二和第三处理一起喷射第四处理气体根据第二喷射时间和/或第二暂停时间，在第三过程期间将气体进入处理室，以在下层形成上层，并且在第四过程期间将第二处理气体注入到处理室中，其中，在第二次消除期间将第二工艺气体注入到处理室中。

38. 发明申请

US20100248442A1 METHODS OF FORMING A PHASE CHANGE MEMORY DEVICE 有权
标题翻译：形成相变存储器件的方法
公开(公告)号：US20100248442A1
公开(公告)日：2010-09-30
申请号：US12731637
申请日：2010-03-25
申请人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
发明人： Jin-Il Lee , Urazaev Vladimir , Jin-Ha Jeong , Seung-Back Shin , Sung-Lae Cho , Hyeong-Geun An , Dong-Hyun Im , Young-Lim Park , Jung-Hyeon Kim
IPC分类号： H01L21/02
CPC分类号： H01L45/1616 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.
摘要翻译：提供形成相变存储器件的方法。可以制备具有下电极和层间绝缘层的半导体器件。下电极可以被层间绝缘层包围。可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。源气体可以同时注入到处理室中。相变材料层可以通过层间绝缘层与下电极接触。可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。可以在相变存储单元上形成上电极。

39. 发明申请

US20090233421A1 Methods of Fabricating Semiconductor Device Including Phase Change Layer 有权
标题翻译：制造包括相变层的半导体器件的方法
公开(公告)号：US20090233421A1
公开(公告)日：2009-09-17
申请号：US12405408
申请日：2009-03-17
申请人： Jin-Il Lee , Sung-Lae Cho , Ik-Soo Kim , Hye-Young Park , Do-Hyung Kim , Dong-Hyun Im
发明人： Jin-Il Lee , Sung-Lae Cho , Ik-Soo Kim , Hye-Young Park , Do-Hyung Kim , Dong-Hyun Im
IPC分类号： H01L21/20
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1616
摘要： Provided are methods of fabricating a semiconductor device including a phase change layer. Methods may include forming a dielectric layer on a substrate, forming an opening in the dielectric layer and depositing, on the substrate having the opening, a phase change layer that contains an element that lowers a process temperature of a thermal treatment process to a temperature that is lower than a melting point of the phase change layer. Methods may include migrating a portion of the phase change layer from outside the opening, into the opening by the thermal treatment process that includes the process temperature that is lower than the melting point of the phase change layer.
摘要翻译：提供制造包括相变层的半导体器件的方法。方法可以包括在衬底上形成电介质层，在电介质层中形成开口，并在具有开口的衬底上沉积相变层，该相变层含有将热处理工艺的工艺温度降低到低于相变层的熔点。方法可以包括通过包括低于相变层的熔点的工艺温度的热处理工艺将一部分相变层从开口外部迁移到开口中。

40. 发明授权

US07485559B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07485559B2
公开(公告)日：2009-02-03
申请号：US11149153
申请日：2005-06-10
申请人： Sung-Lae Cho , Horii Hideki
发明人： Sung-Lae Cho , Horii Hideki
IPC分类号： H01L21/44
CPC分类号： H01L21/76886 , H01L27/115 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： A semiconductor device and methods thereof. The semiconductor device includes a first layer formed on a substrate, the first layer having a higher conductivity. The semiconductor device further includes a second layer formed on the first layer, the second layer including a hole exposing a portion of the first layer, the exposed portion of the first layer having a lower conductivity. The method includes forming a first layer on a substrate, the first layer having a higher conductivity, forming a second layer on the first layer, exposing a portion of the first layer by forming a hole in the second layer, performing a process on at least the exposed portion of the first layer, the process decreasing the conductivity of the exposed portion. The exposed portion including the lower conductivity or higher resistivity may block heat from conducting in the first layer.
摘要翻译：半导体器件及其方法。半导体器件包括形成在衬底上的第一层，第一层具有较高的导电性。半导体器件还包括形成在第一层上的第二层，第二层包括暴露第一层的一部分的孔，第一层的暴露部分具有较低的导电性。该方法包括在衬底上形成第一层，第一层具有较高的导电性，在第一层上形成第二层，通过在第二层中形成孔露出第一层的一部分，至少执行一个工艺第一层的暴露部分，该工艺降低了暴露部分的导电性。包括较低电导率或较高电阻率的暴露部分可阻止第一层中导热的热量。

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