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31. 发明申请

US20080286972A1 ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST 有权
标题翻译：添加沉积物中的多氯硅烷蚀刻阻垢剂
公开(公告)号：US20080286972A1
公开(公告)日：2008-11-20
申请号：US12170634
申请日：2008-07-10
申请人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Timothy J. Dalton , Wesley C. Natzle , Paul W. Pastel , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/308
CPC分类号： H01L21/32139 , H01L21/32137 , Y10S438/909
摘要： A chemical composition and method for providing uniform and consistent etching of gate stacks on a semiconductor wafer, whereby the composition includes an etchant and an added ballast gas added. The gate stacks are formed using this combined etchant and ballast gas composition. The ballast gas may either be similar to, or the equivalent of, a gaseous byproduct generated within the processing chamber. The ballast gas is added in either an overload amount, or in an amount sufficient to compensate for varying pattern factor changes across the water. This etchant and added ballast gas form a substantially homogeneous etchant across the entire wafer, thereby accommodating for or compensating for these pattern factor differences. When etching the wafer using this homogeneous etchant, a passivation layer is formed on exposed wafer surfaces. The passivation layer protects the lateral sidewalls of the gate stacks during etch to result in straighter gate stacks.
摘要翻译：一种用于在半导体晶片上提供均匀且一致的栅叠层蚀刻的化学组成和方法，由此所述组合物包括添加的蚀刻剂和添加的压载气体。使用这种组合的蚀刻剂和压载气组合物形成栅堆叠。压载气体可以类似于或等同于在处理室内产生的气态副产物。压载气体以过载量或足以补偿横跨水的变化因子变化的量加入。这种蚀刻剂和添加的压载气体在整个晶片上形成基本均匀的蚀刻剂，从而适应或补偿这些图案因子差异。当使用这种均匀的蚀刻剂蚀刻晶片时，在暴露的晶片表面上形成钝化层。钝化层在蚀刻期间保护栅极堆叠的侧壁以产生更直的栅叠层。

32. 发明申请

US20070275510A1 METAL OXIDE FIELD EFFECT TRANSISTOR WITH A SHARP HALO AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有夏普HALO的金属氧化物场效应晶体管和形成晶体管的方法
公开(公告)号：US20070275510A1
公开(公告)日：2007-11-29
申请号：US11420318
申请日：2006-05-25
申请人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
发明人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
IPC分类号： H01L21/8232 , H01L21/8234 , H01L21/335
CPC分类号： H01L29/66636 , H01L29/6659 , H01L29/7833
摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.
摘要翻译：公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。蚀刻半导体层以形成切割栅极介电层的凹部。低能量植入物形成晕轮。然后，执行COR预清洁，并且通过外延沉积填充凹部。外延可以被原位掺杂或随后植入以形成源/漏扩展。或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。

33. 发明授权

US09016236B2 Method and apparatus for angular high density plasma chemical vapor deposition 有权
标题翻译：用于角高密度等离子体化学气相沉积的方法和装置
公开(公告)号：US09016236B2
公开(公告)日：2015-04-28
申请号：US12185339
申请日：2008-08-04
申请人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
发明人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
IPC分类号： H01L21/306 , C23C16/00 , C23C16/507 , C23C16/34 , C23C16/40 , C23C16/455 , C23C16/458 , C23C16/56 , H01J37/20 , H01J37/32 , H01L27/108 , H01L21/316 , H01L21/318
CPC分类号： C23C16/507 , C23C16/345 , C23C16/402 , C23C16/45578 , C23C16/4586 , C23C16/56 , H01J37/20 , H01J37/321 , H01J2237/20207 , H01J2237/3323 , H01L21/31608 , H01L21/3185 , H01L27/10867
摘要： A high-density plasma chemical vapor deposition tool and the method for use of the tool is disclosed. The chemical vapor deposition tool allows for angular adjustment of the pedestal that holds the substrate being manufactured. Electromagnets serve as an “electron filter” that allows for angular deposition of material onto the substrate. Methods for fabrication of trench structures and asymmetrical spacers in a semiconductor manufacturing process are also disclosed. The angular deposition saves process steps, thereby reducing time, complexity, and cost of manufacture, while improving overall product yield.
摘要翻译：公开了一种高密度等离子体化学气相沉积工具和该工具的使用方法。化学气相沉积工具允许对保持正在制造的衬底的基座进行角度调节。电磁铁用作允许将材料角度沉积到衬底上的“电子过滤器”。还公开了在半导体制造工艺中制造沟槽结构和不对称间隔物的方法。角度沉积节省了工艺步骤，从而降低了制造时间，复杂性和成本，同时提高了整体产品的产量。

34. 发明授权

US08507375B1 Alignment tolerant semiconductor contact and method 有权
标题翻译：对准耐受半导体接触和方法
公开(公告)号：US08507375B1
公开(公告)日：2013-08-13
申请号：US13364976
申请日：2012-02-02
申请人： André P. Labonté , Richard S. Wise
发明人： André P. Labonté , Richard S. Wise
IPC分类号： H01L21/44
CPC分类号： H01L21/28247 , H01L21/76814 , H01L21/76888 , H01L21/76897 , H01L29/66545
摘要： An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
摘要翻译：通过提供其上具有上表面的第一导电区域（例如，MOSFET栅极）的衬底来形成对准容限的电接触，所述第一导电区域被第一介电区域横向界定，施加具有部分地覆盖在衬底上并在上表面的一部分上的接触区域（例如，用于MOSFET源极或漏极）上的开口，形成通过延伸到接触区域和上表面的部分的第一介电区域的通道，从而暴露接触区域和上表面的一部分，将上表面的一部分转换成第二电介质区域，并且用与接触区域电接触但与导电区域电绝缘的导体填充开口电介质区域。

35. 发明申请

US20120306093A1 CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE 有权
标题翻译：将金属掩模转换为金属氧化物蚀刻停止层和相关半导体结构
公开(公告)号：US20120306093A1
公开(公告)日：2012-12-06
申请号：US13151646
申请日：2011-06-02
申请人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
发明人： Brett H. Engel , Ying Li , Viraj Y. Sardesai , Richard S. Wise
IPC分类号： H01L21/283 , H01L23/48 , B82Y40/00 , B82Y99/00
CPC分类号： H01L21/31144 , H01L21/02178 , H01L21/02244 , H01L21/02252 , H01L21/76804 , H01L21/7681 , H01L21/76829
摘要： A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices.
摘要翻译：一种方法包括提供包括多个装置的半导体结构; 在所述半导体结构上沉积氮化物盖; 在所述氮化物盖上形成铝掩模，所述铝掩模包括多个第一开口; 将铝掩模转变成氧化铝蚀刻停止层; 并执行中间线制造处理，将氧化铝蚀刻停止层留在原位。半导体结构在基板上包括多个器件; 多个装置上的氮化物盖; 在氮化物盖上方的氧化铝蚀刻停止层; 氧化铝蚀刻停止层上的层间电介质（ILD）; 以及穿过ILD延伸的多个触点，氧化铝蚀刻停止层和氮化物帽到多个器件。

36. 发明授权

US08193099B1 Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing 有权
标题翻译：保护暴露的金属栅极结构免受集成电路制造中的蚀刻工艺
公开(公告)号：US08193099B1
公开(公告)日：2012-06-05
申请号：US13049933
申请日：2011-03-17
申请人： Mukesh V. Khare , Renee T. Mo , Ravikumar Ramachandran , Richard S. Wise , Hongwen Yan
发明人： Mukesh V. Khare , Renee T. Mo , Ravikumar Ramachandran , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/823437 , H01L21/823481 , H01L21/823828 , H01L21/823878
摘要： A method of forming a semiconductor device includes forming a transistor gate stack over a substrate having an active area and a shallow trench isolation (STI) region. First sidewall spacers are formed on the transistor gate stack, and an isotropic etch process is applied to isotropically remove an excess portion of a metal layer included within the transistor gate stack, the excess portion left unprotected by the first sidewall spacers. Second sidewall spacers are formed on the transistor gate stack, the second sidewall spacers completely encapsulating the metal layer of the transistor gate stack.
摘要翻译：形成半导体器件的方法包括在具有有源区和浅沟槽隔离（STI）区的衬底上形成晶体管栅叠。第一侧壁间隔物形成在晶体管栅极堆叠上，并且各向同性蚀刻工艺被应用于各向同性地去除包括在晶体管栅极叠层内的金属层的过剩部分，剩余部分未被第一侧壁间隔物保护。第二侧壁间隔物形成在晶体管栅极叠层上，第二侧壁间隔物完全封装晶体管栅极叠层的金属层。

37. 发明授权

US07498271B1 Nitrogen based plasma process for metal gate MOS device 有权
标题翻译：金属栅MOS器件的氮基等离子体工艺
公开(公告)号：US07498271B1
公开(公告)日：2009-03-03
申请号：US12145035
申请日：2008-06-24
申请人： Ricardo A. Donaton , Rashmi Jha , Siddarth A. Krishnan , Xi Li , Renee T. Mo , Naim Moumen , Wesley C. Natzle , Ravikumar Ramachandran , Richard S. Wise
发明人： Ricardo A. Donaton , Rashmi Jha , Siddarth A. Krishnan , Xi Li , Renee T. Mo , Naim Moumen , Wesley C. Natzle , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L21/31
CPC分类号： H01L21/31138 , H01L21/28202 , H01L21/31155 , H01L21/823828 , H01L21/823878 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.
摘要翻译：本发明在一个实施例中提供了一种形成栅极结构的方法，该栅极结构包括提供包括半导体器件区域的衬底，在半导体器件区域顶部存在的高k电介质材料以及高k电介质顶部的金属栅极导体材料，在金属栅极导体顶上施加光致抗蚀剂层; 图案化光致抗蚀剂层以提供覆盖对应于栅极堆叠的金属栅极导体的一部分的蚀刻掩模; 蚀刻对蚀刻掩模有选择性的金属栅极导体和高k电介质材料; 并用基本上不含氧的氮气等离子体去除蚀刻掩模。

38. 发明授权

US06838347B1 Method for reducing line edge roughness of oxide material using chemical oxide removal 失效
标题翻译：使用化学氧化物去除减少氧化物材料的线边缘粗糙度的方法
公开(公告)号：US06838347B1
公开(公告)日：2005-01-04
申请号：US10605331
申请日：2003-09-23
申请人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
发明人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
IPC分类号： H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31116
摘要： A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.

39. 发明授权

US06656375B1 Selective nitride: oxide anisotropic etch process 失效
标题翻译：选择性氮化物：氧化物各向异性蚀刻工艺
公开(公告)号：US06656375B1
公开(公告)日：2003-12-02
申请号：US09014806
申请日：1998-01-28
申请人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
发明人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
IPC分类号： C23F100
CPC分类号： H01L21/31116
摘要： An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.
摘要翻译：用于衬底的氮化物层的各向异性蚀刻工艺，该方法包括使用包含富氢氟代烃，氧化剂和碳源的蚀刻剂气体。富氢氟烃优选为CH 3 F或CH 2 F 2之一，碳源优选为CO 2或CO之一，氧化剂优选为O 2。氟烃优选以约7％-35体积％存在于气体中，氧化剂优选以约1％-35％体积的比例存在于气体中，并且碳源优选以约30％的比例存在于气体中， -92％。

40. 发明授权

US06355567B1 Retrograde openings in thin films 失效
标题翻译：薄膜逆行开口
公开(公告)号：US06355567B1
公开(公告)日：2002-03-12
申请号：US09345646
申请日：1999-06-30
申请人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
发明人： Scott D. Halle , Paul C. Jamison , David E. Kotecki , Richard S. Wise
IPC分类号： H01L21311
CPC分类号： H01L21/76879 , H01L21/31116 , H01L21/76804 , H01L21/7682 , H01L21/76885
摘要： Retrograde openings in thin films and the process for forming the same. The openings may include conductive materials formed within the openings to serve as a wiring pattern which includes wires having tapered cross sections. The process involves a two-step etching procedure for forming a retrograde opening within a film having a gradient of a characteristic that influences the etch rate for a chosen etchant species. An opening is first formed within the film by an anisotropic etch process. The opening is then converted to an opening including retrograde features by an isotropic etch process which is selective to the characteristic. Thereafter, the retrograde opening is filled with a conductive material, in one case, by electroplating or other deposition techniques.
摘要翻译：薄膜中的逆行开口及其形成方法。开口可以包括形成在开口内的导电材料，以用作包括具有锥形横截面的导线的布线图案。该方法涉及用于在膜内形成具有影响所选择的蚀刻剂物质的蚀刻速率的特性梯度的逆向开口的两步蚀刻方法。首先通过各向异性蚀刻工艺在膜内形成开口。然后通过对特性有选择性的各向同性蚀刻工艺将开口转换成包括逆行特征的开口。此后，逆行开口填充有导电材料，在一种情况下，通过电镀或其它沉积技术。

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