会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 34. 发明授权
    • Method for synchronization through accelerated advance of counters
    • 通过加速计数器进行同步的方法
    • US07260165B2
    • 2007-08-21
    • US10638293
    • 2003-08-12
    • Kevin MillerAnders Hebsgaard
    • Kevin MillerAnders Hebsgaard
    • H04L7/00
    • H04N21/6168H04J3/0682H04L47/50H04N7/17309H04N21/242
    • A method for synchronizing counters in a terminal device, such as a cable modem in a DOCSIS-based system, with those of an administrative device, such as a headend. A cable modem advances its frame counter. With each increment of the frame counter, the cable modem's minislot counter advances by an amount equal to the number of minislots per frame. Likewise, with each increment of the frame counter, the cable modem's timestamp counter is incremented by the number of timestamps per frame. This continues until the counters at the cable modem are within one frame of the headend's counters. The minislot counter is then incremented. With each increment of the minislot counter, the timestamp counter is incremented by an amount equal to the number of timestamps per minislot. This continues until the cable modem's counters are within a minislot of the headend's counters. The timestamp counter is then incremented until the cable modem's counters match those of the headend.
    • 一种用于将终端设备中的计数器(例如基于DOCSIS的系统中的电缆调制解调器)与诸如头端的管理设备的计数器同步的方法。 电缆调制解调器前进其帧计数器。 随着帧计数器的每个增量,电缆调制解调器的小时隙计数器前进一个等于每帧的微时隙数量的数量。 类似地,对于帧计数器的每个增量,电缆调制解调器的时间戳计数器增加每帧的时间戳的数量。 这一直延续到电缆调制解调器的计数器位于头端计数器的一个帧内。 然后增加微型计数器。 对于小时隙计数器的每个增量,时间戳计数器增加等于每个小时隙的时间戳数的量。 这一直延续到电缆调制解调器的计数器位于前端计数器的一小段时间内。 然后,时间戳计数器递增,直到电缆调制解调器的计数器与前端的计数器匹配。
    • 38. 发明申请
    • Nonlinear mapping in digital-to-analog and analog-to-digital converters
    • 数模转换器和模数转换器的非线性映射
    • US20050270203A1
    • 2005-12-08
    • US11124394
    • 2005-05-09
    • Todd BrooksKevin MillerJosephus Van Engelen
    • Todd BrooksKevin MillerJosephus Van Engelen
    • H03M3/00H03M7/36
    • H03M7/3013
    • In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.
    • 在高保真数字调制器中,提供映射器以最小化多个数模转换器或模数转换器之间的量化噪声,抖动和串扰。 映射器从量化器接收量化电平,并将量化电平映射到输出序列。 映射器包括定义对应于每个量化级别的多个序列的表。 每个序列包括具有多个值之一的两个或多个符号。 映射器还包括选择多个序列之一作为输出序列的发生器。 第一个输出序列的最后一个符号等于下一个输出序列的第一个符号,依此类推。 发生器通过在接收到的每个量化级别的第一和第二序列之间交替来选择输出序列。 发生器通过在接收到的每个奇数值量化电平具有正和负共模能量的序列之间交替来选择输出序列。