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1. 发明授权

US07058864B1 Test for processor memory cache 失效
标题翻译：测试处理器内存缓存
公开(公告)号：US07058864B1
公开(公告)日：2006-06-06
申请号：US10442453
申请日：2003-05-21
申请人： William Bryson McHardy , Raymond Paul Gratias , Kevin Miller , Brian Nugent
发明人： William Bryson McHardy , Raymond Paul Gratias , Kevin Miller , Brian Nugent
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G06F12/0802 , G11C2029/0407
摘要： Systems, methods, software products test a memory cache of a processor that includes a test engine (e.g., a BISTE). High level test source code is formulated to use routines in API source code that, when compiled into machine test code, interfaces with the test engine. The machine test code is executed with the processor to test the memory cache to detect one or more faulty memory blocks in the memory cache. If any of the faulty memory blocks are detected, the test engine is instructed, through the machine test code, to set one or more bits in registers to functionally replace the faulty memory blocks with redundant blocks of the memory cache.
摘要翻译：系统，方法，软件产品测试包括测试引擎（例如BISTE）的处理器的存储器缓存。高级测试源代码被用于在API源代码中使用例程，当编译成机器测试代码时，与测试引擎的接口。机器测试代码与处理器一起执行，以测试存储器高速缓存以检测存储器高速缓存中的一个或多个故障存储器块。如果检测到任何错误的存储器块，则通过机器测试代码来指示测试引擎在寄存器中设置一个或多个位，以使用存储器高速缓存的冗余块功能地替换故障存储器块。

2. 发明授权

US06711730B2 Synthesizing signal net information from multiple integrated circuit package models 失效
标题翻译：从多个集成电路封装模型合成信号网络信息
公开(公告)号：US06711730B2
公开(公告)日：2004-03-23
申请号：US10179077
申请日：2002-05-13
申请人： Mark D. Frank , William Bryson McHardy , Peter Shaw Moldauer
发明人： Mark D. Frank , William Bryson McHardy , Peter Shaw Moldauer
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06Q40/00
摘要： Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.
摘要翻译：公开了用于从多个计算机可读集成电路封装模型自动合成信息的技术。在一个实施例中，多个包模型中的每一个包含描述不同包的信息。这样的信息可以包括例如模拟包装中的信号网络的包装内路径长度和/或传播延迟。公开了用于自动合成这样的信息以产生跨越所有建模包装的信号网络的聚合路径长度和/或传播延迟的技术。即使当包装模型使用相互不一致的信号网络命名约定时，也可以执行这种合成，并且所建模的包由不同的材料组成。还公开了向包装设计者提供信息以帮助包装设计者改进包装模型的设计的技术。

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