专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07533243B2 Processor for executing highly efficient VLIW 有权
公开(公告)号：US07533243B2
公开(公告)日：2009-05-12
申请号：US10097759
申请日：2002-05-22
申请人： Shuichi Takayama , Nobuo Higaki
发明人： Shuichi Takayama , Nobuo Higaki
IPC分类号： G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/383 , G06F9/3853
摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

32. 发明申请

US20080141229A1 PROCESSOR, PROGRAM CONVERSION APPARATUS, PROGRAM CONVERSION METHOD, AND COMPUTER PROGRAM 审中-公开
标题翻译：处理器，程序转换装置，程序转换方法和计算机程序
公开(公告)号：US20080141229A1
公开(公告)日：2008-06-12
申请号：US11969083
申请日：2008-01-03
申请人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
发明人： Taketo Heishi , Hajime Ogawa , Shuichi Takayama , Toshiyuki Sakata , Shohei Michimoto
IPC分类号： G06F9/45 , G06F9/312
CPC分类号： G06F9/30094 , G06F9/30021 , G06F9/30072
摘要： The first, second, and third operating units 441 to 443 each perform a predetermined operation according to an instruction before a point of time partway through a clock cycle. When having performed a comparison operation, each operating unit outputs a result value to the condition flag operating unit 51. The condition flag operating unit 51 calculates a new condition flag value by performing a logical operation on either (a) a value that has been read from the condition flag register 46 and the result value or (b) the result values themselves. The condition flag operating unit 51 outputs, before the clock cycle ends, the new condition flag value to one of the first, second, and third gates 451 to 453 that is related to a conditional instruction so as to control nullification of the conditional new condition flag value.
摘要翻译：第一，第二和第三操作单元441至443各自根据在时钟周期的中途的时间点之前的指令执行预定的操作。当执行比较操作时，每个操作单元将结果值输出到条件标志操作单元51。条件标志操作单元51通过对（a）从条件标志寄存器46读取的值和结果值或（b）结果值本身执行逻辑运算来计算新条件标志值。条件标志操作单元51在时钟周期结束之前将新条件标志值输出到与条件指令相关的第一，第二和第三门451至453中的一个，以便控制条件新条件的无效标志值。

33. 发明申请

US20070231901A1 Microfluidic cell culture media 审中-公开
标题翻译：微流体细胞培养基
公开(公告)号：US20070231901A1
公开(公告)日：2007-10-04
申请号：US11607388
申请日：2006-12-01
申请人： Shuichi Takayama , Nobuyuki Futai , Yun Heo , Gary Smith , Jonathan Song
发明人： Shuichi Takayama , Nobuyuki Futai , Yun Heo , Gary Smith , Jonathan Song
IPC分类号： C12N1/20 , C12N5/00
CPC分类号： C12N1/38 , B01L3/5027 , C12M23/16 , C12M23/34
摘要： A microfluidic cell culture media may have an initial concentration of an active material less than a therapeutic window of concentration necessary to provide a cellular mass a therapeutic environment.
摘要翻译：微流体细胞培养基可以具有小于提供细胞群体治疗环境所必需的浓度的治疗窗口的活性物质的初始浓度。

34. 发明申请

US20060270021A1 Integrated microfluidic sperm isolation and insemination device 审中-公开
标题翻译：集成微流体精子分离和授精装置
公开(公告)号：US20060270021A1
公开(公告)日：2006-11-30
申请号：US10559742
申请日：2004-06-07
申请人： Shuichi Takayama , Gary Smith , Ronald Suh
发明人： Shuichi Takayama , Gary Smith , Ronald Suh
IPC分类号： C12M1/00
CPC分类号： B01L3/50273 , B01L3/502753 , B01L3/502776 , B01L2200/0636 , B01L2400/0487
摘要： An integrated microfluidic sperm isolation and oocyte insemination device provides the opportunity to perform in vitro insemination with motilityenhanced sperm samples and with minimal manipulation of fragile oocytes. Sperm sorting is performed in a common sort channel wherein more mobile sperm swim across the interface between co-laminar flows of semen and media fluid.
摘要翻译：整合的微流体精子分离和卵母细胞授精装置提供了运动增强的精子样品进行体外授精并且对脆弱的卵母细胞进行最小操作的机会。精子分选在通常的分类通道中进行，其中更多的移动精子游动穿过精液和培养基流体的共层流之间的界面。

35. 发明申请

US20060166357A1 Integrated microfludic control employing programmable tactile actuators 有权
标题翻译：采用可编程触觉执行器的集成微电极控制
公开(公告)号：US20060166357A1
公开(公告)日：2006-07-27
申请号：US10548692
申请日：2004-03-10
申请人： Shuichi Takayama , Xiaoyue Zhu , Wei Gu , Gary Smith , Yunseok Heo , Brenda Cho , Nobuyuki Futai
发明人： Shuichi Takayama , Xiaoyue Zhu , Wei Gu , Gary Smith , Yunseok Heo , Brenda Cho , Nobuyuki Futai
IPC分类号： C12M3/00
CPC分类号： B01L3/50273 , B01J2219/00396 , B01J2219/00891 , B01L3/502738 , B01L2200/10 , B01L2200/12 , B01L2200/143 , B01L2300/025 , B01L2300/044 , B01L2300/0816 , B01L2300/0867 , B01L2300/0877 , B01L2300/0887 , B01L2300/123 , B01L2400/0481 , B01L2400/0638 , B01L2400/0655 , C12M23/16 , F16K99/0001 , F16K99/0026 , F16K99/0048 , F16K2099/0074 , F16K2099/0078 , F16K2099/008 , F16K2099/0084 , G09B23/12
摘要： Microfluidic devices having active features such as valves, peristaltic pumps, and mixing portions are fabricated to have a thin elastomeric membrane over the active features. The active features are activated by a tactile actuator external to the membrane, for example, a commercial Braille display. The display may be computer controlled, for example by simple text editor software, to activate individual Braille protrusions or a plurality of protrusions to actuate the active portions of the microfluidic device. Integral devices can incorporate the tactile actuators in a single device, but still external to the membrane.
摘要翻译：具有诸如阀，蠕动泵和混合部分的主动特征的微流体装置被制造成在活性特征上具有薄的弹性膜。主动特征由膜外部的触觉致动器激活，例如商业盲文显示器。显示器可以是计算机控制的，例如通过简单的文本编辑器软件来激活单个盲文突起或多个突起来致动微流体装置的有效部分。整体设备可以将触觉致动器结合在单个设备中，但仍然在膜的外部。

36. 发明授权

US07076638B2 Processor, compiler and compilation method 有权
公开(公告)号：US07076638B2
公开(公告)日：2006-07-11
申请号：US10246482
申请日：2002-09-19
申请人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
发明人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30072 , G06F9/3822
摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

37. 发明授权

US07073169B2 Compiler device with branch instruction inserting unit 有权
标题翻译：具有分支指令插入单元的编译器
公开(公告)号：US07073169B2
公开(公告)日：2006-07-04
申请号：US10174108
申请日：2002-06-17
申请人： Hajime Ogawa , Shuichi Takayama , Taketo Heishi , Nobuo Higaki
发明人： Hajime Ogawa , Shuichi Takayama , Taketo Heishi , Nobuo Higaki
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section. Thus, a compiler device employing conditional executable instructions is provided that is capable of generating an assembler code that does not degrade the performance when the instructions are executed, even if a source program includes a branch instruction that causes a then part and an else part to be executed through unbalanced numbers of cycles, respectively.
摘要翻译：编译器装置包括条件可执行指令生成单元和分支指令插入单元。条件可执行指令生成单元生成当满足条件可执行指令引用的条件时执行的条件可执行指令。在存在包含在一个周期或多个周期中不执行指令的非执行条件的部分的情况下，分支指令插入单元插入参考非执行条件的条件分支指令，并且指示在该部分的最后一个周期之后立即分支到一个周期，直到在该部分开始之前的一个周期的指令之后。因此，提供了一种使用条件可执行指令的编译器装置，其能够生成当执行指令时不降低性能的汇编代码，即使源程序包括分支指令，该分支指令导致随后的部分和其他部分分别通过不平衡的周期数执行。

38. 发明申请

US20060031661A1 Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor 有权
标题翻译：读取用于以与wihcih指令中的单元无关的单元执行指令的处理器，以及用于这种处理器的编译器，优化装置，汇编器，链接器，调试器和反汇编器
公开(公告)号：US20060031661A1
公开(公告)日：2006-02-09
申请号：US11245357
申请日：2005-10-07
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/40
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

39. 发明授权

US06904135B2 Compound device and telephone station device connected to the same, and power supply system and portable telephone system using compound device 失效
标题翻译：复合设备和电话站设备连接在一起，电源系统和便携式电话系统使用复合设备
公开(公告)号：US06904135B2
公开(公告)日：2005-06-07
申请号：US10172216
申请日：2002-06-14
申请人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
发明人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
IPC分类号： H04B1/38 , H04B7/26 , H04M1/00 , H04M1/723 , H04M1/725 , H04N5/44 , H04W4/24 , H04W76/02 , H04W88/02 , H04W88/08 , H04W88/14 , H04M11/00 , H04B1/00
CPC分类号： H04B1/005 , H04B1/3805 , H04M1/725 , H04N5/4401 , H04N21/2408 , H04N21/2543 , H04N21/4126 , H04N21/4263 , H04N21/42676 , H04N21/433 , H04N21/43637 , H04N21/44227 , H04N21/443 , H04N21/6112 , H04N21/6162 , H04N21/6168 , H04N21/654 , H04N21/6582 , H04N21/6583
摘要： A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.
摘要翻译：复合设备具有数字电视的结构硬件，连接到天线和电话台，并且通过读取和运行数字电视（DTV）程序或使用通用处理器的基站程序，它具有数字电视的功能和便携式电话基站的功能。复合设备的所有者根据通信记录部分中的记录，收到其订阅的电话费或其电费的折扣。因此，提供了数字电视机被赋予便携式电话基站的功能的复合装置，从而可以实现基站的不足之处，不需要设备投资支出和便携式设备所有者的新颖的基础设施给予经济利益，允许公共使用私人拥有作为便携式电话基站。

40. 发明申请

US20050091478A1 Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 审中-公开
标题翻译：处理器使用较少的硬件和指令转换设备减少指令类型的数量
公开(公告)号：US20050091478A1
公开(公告)日：2005-04-28
申请号：US10617506
申请日：2003-07-11
申请人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
发明人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/45 , G06F9/00
CPC分类号： G06F9/30058 , G06F8/447 , G06F9/30021 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F9/3842
摘要： A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.
摘要翻译：解码并执行指令序列的处理器包括：状态保持单元，用于当执行预定指令时，保持所述预定指令的执行结果的更新状态; 获取单元，用于获得指令序列，所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合，其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥，第二条件指令，其具有与第一条件指令相同的操作码，指令集不被分配第二条件指令，以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元，用于逐个地解码所获得的指令序列中的每个指令; 判断单元，用于当解码单元解码第一条件指令时，判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元，用于仅当判断单元的判断结果为肯定时，执行由解码单元解码的第一条件指令中由操作码指定的操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式