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1. 发明授权

US06880150B1 PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR 有权
标题翻译：执行单元中指令的处理程序，与指令读取的单元相关，以及编译器，优化设备，汇编器，链接器，调试器和此类处理器的分解器
公开(公告)号：US06880150B1
公开(公告)日：2005-04-12
申请号：US09301284
申请日：1999-04-28
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a〜409c解码分支指令时，分支指令中包含的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

2. 发明授权

US06397319B1 Process for executing highly efficient VLIW 有权
标题翻译：执行高效率VLIW的过程
公开(公告)号：US06397319B1
公开(公告)日：2002-05-28
申请号：US09598397
申请日：2000-06-20
申请人： Shuichi Takayama , Nobuo Higaki
发明人： Shuichi Takayama , Nobuo Higaki
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/383 , G06F9/3853
摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
摘要翻译： 32位指令50由4位格式字段51，4位操作字段52和2位12位操作字段59和60组成.4位操作字段52只能包括（1）指示使用隐含指示的常数寄存器36的存储值作为分支地址的分支操作的操作代码“cc”，或者（2）常数“const”。 4位操作字段52的内容由格式字段51中提供的格式代码指定。

3. 发明授权

US5928358A Information processing apparatus which accurately predicts whether a branch is taken for a conditional branch instruction, using small-scale hardware 失效
标题翻译：使用小规模硬件来准确地预测分支是否用于条件分支指令的信息处理装置
公开(公告)号：US5928358A
公开(公告)日：1999-07-27
申请号：US987260
申请日：1997-12-09
申请人： Shuichi Takayama , Nobuo Higaki
发明人： Shuichi Takayama , Nobuo Higaki
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3844
摘要： A branch instruction includes a set of branch prediction information 13b and a set of branch history information 13c. The set of branch prediction information 13b is made up of 1 bit which predicts whether a branch will be performed during the next execution of the instruction. The set of branch history information 13c is made up of 2 bits showing a frequency, with which the branch has been taken, is "very high", "high", "low" or "very low". An instruction fetching unit 12 prefetches an instruction from a cache memory 11a in accordance with the set of branch prediction information 13b. After an instruction executing unit 15 completes an execution of the branch instruction, a branch history information generating unit 16 generates a new set of branch history information and a branch prediction information generating unit 17 generates a new set of branch prediction information, in accordance with the execution result and the preceding branch history information 13c. A branch instruction updating unit 18 overwrites the generated set of branch history information and the generated set of branch prediction information on the corresponding branch instruction stored in the main memory 11a.
摘要翻译：分支指令包括一组分支预测信息13b和一组分支历史信息13c。分支预测信息组13b由1比特组成，该比特预测在下一次执行指令期间是否执行分支。分支历史信息13c由2比特构成，分支被采用的频率为“非常高”，“高”，“低”或“非常低”。指令取出单元12根据分支预测信息组13b预取来自高速缓存存储器11a的指令。在指令执行单元15完成分支指令的执行之后，分支历史信息生成单元16生成一组新的分支历史信息，并且分支预测信息生成单元17根据该分支预测信息生成单元17生成一组新的分支预测信息执行结果和前一分支历史信息13c。分支指令更新单元18对存储在主存储器11a中的相应分支指令重写所生成的分支历史信息和所生成的分支预测信息组。

4. 发明授权

US08019971B2 Processor for executing highly efficient VLIW 有权
标题翻译：用于执行高效率VLIW的处理器
公开(公告)号：US08019971B2
公开(公告)日：2011-09-13
申请号：US12418965
申请日：2009-04-06
申请人： Shuichi Takayama , Nobuo Higaki
发明人： Shuichi Takayama , Nobuo Higaki
IPC分类号： G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/383 , G06F9/3853
摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
摘要翻译： 32位指令50由4位格式字段51，4位操作字段52和2位12位操作字段59和60组成.4位操作字段52只能包括（1）指示使用隐含指示的常数寄存器36的存储值作为分支地址的分支操作的操作代码“cc”，或者（2）常数“const”。 4位操作字段52的内容由格式字段51中提供的格式代码指定。

5. 发明授权

US07533243B2 Processor for executing highly efficient VLIW 有权
公开(公告)号：US07533243B2
公开(公告)日：2009-05-12
申请号：US10097759
申请日：2002-05-22
申请人： Shuichi Takayama , Nobuo Higaki
发明人： Shuichi Takayama , Nobuo Higaki
IPC分类号： G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/383 , G06F9/3853
摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

6. 发明授权

US07076638B2 Processor, compiler and compilation method 有权
公开(公告)号：US07076638B2
公开(公告)日：2006-07-11
申请号：US10246482
申请日：2002-09-19
申请人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
发明人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30072 , G06F9/3822
摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

7. 发明授权

US07073169B2 Compiler device with branch instruction inserting unit 有权
标题翻译：具有分支指令插入单元的编译器
公开(公告)号：US07073169B2
公开(公告)日：2006-07-04
申请号：US10174108
申请日：2002-06-17
申请人： Hajime Ogawa , Shuichi Takayama , Taketo Heishi , Nobuo Higaki
发明人： Hajime Ogawa , Shuichi Takayama , Taketo Heishi , Nobuo Higaki
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section. Thus, a compiler device employing conditional executable instructions is provided that is capable of generating an assembler code that does not degrade the performance when the instructions are executed, even if a source program includes a branch instruction that causes a then part and an else part to be executed through unbalanced numbers of cycles, respectively.
摘要翻译：编译器装置包括条件可执行指令生成单元和分支指令插入单元。条件可执行指令生成单元生成当满足条件可执行指令引用的条件时执行的条件可执行指令。在存在包含在一个周期或多个周期中不执行指令的非执行条件的部分的情况下，分支指令插入单元插入参考非执行条件的条件分支指令，并且指示在该部分的最后一个周期之后立即分支到一个周期，直到在该部分开始之前的一个周期的指令之后。因此，提供了一种使用条件可执行指令的编译器装置，其能够生成当执行指令时不降低性能的汇编代码，即使源程序包括分支指令，该分支指令导致随后的部分和其他部分分别通过不平衡的周期数执行。

8. 发明申请

US20060031661A1 Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor 有权
标题翻译：读取用于以与wihcih指令中的单元无关的单元执行指令的处理器，以及用于这种处理器的编译器，优化装置，汇编器，链接器，调试器和反汇编器
公开(公告)号：US20060031661A1
公开(公告)日：2006-02-09
申请号：US11245357
申请日：2005-10-07
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/40
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

9. 发明授权

US06904135B2 Compound device and telephone station device connected to the same, and power supply system and portable telephone system using compound device 失效
标题翻译：复合设备和电话站设备连接在一起，电源系统和便携式电话系统使用复合设备
公开(公告)号：US06904135B2
公开(公告)日：2005-06-07
申请号：US10172216
申请日：2002-06-14
申请人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
发明人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
IPC分类号： H04B1/38 , H04B7/26 , H04M1/00 , H04M1/723 , H04M1/725 , H04N5/44 , H04W4/24 , H04W76/02 , H04W88/02 , H04W88/08 , H04W88/14 , H04M11/00 , H04B1/00
CPC分类号： H04B1/005 , H04B1/3805 , H04M1/725 , H04N5/4401 , H04N21/2408 , H04N21/2543 , H04N21/4126 , H04N21/4263 , H04N21/42676 , H04N21/433 , H04N21/43637 , H04N21/44227 , H04N21/443 , H04N21/6112 , H04N21/6162 , H04N21/6168 , H04N21/654 , H04N21/6582 , H04N21/6583
摘要： A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.
摘要翻译：复合设备具有数字电视的结构硬件，连接到天线和电话台，并且通过读取和运行数字电视（DTV）程序或使用通用处理器的基站程序，它具有数字电视的功能和便携式电话基站的功能。复合设备的所有者根据通信记录部分中的记录，收到其订阅的电话费或其电费的折扣。因此，提供了数字电视机被赋予便携式电话基站的功能的复合装置，从而可以实现基站的不足之处，不需要设备投资支出和便携式设备所有者的新颖的基础设施给予经济利益，允许公共使用私人拥有作为便携式电话基站。

10. 发明申请

US20050091478A1 Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions 审中-公开
标题翻译：处理器使用较少的硬件和指令转换设备减少指令类型的数量
公开(公告)号：US20050091478A1
公开(公告)日：2005-04-28
申请号：US10617506
申请日：2003-07-11
申请人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
发明人： Shuichi Takayama , Kensuke Odani , Akira Tanaka , Nobuo Higaki , Masato Suzuki , Tetsuya Tanaka , Taketo Heishi , Shinya Miyaji
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/45 , G06F9/00
CPC分类号： G06F9/30058 , G06F8/447 , G06F9/30021 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F9/3842
摘要： A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.
摘要翻译：解码并执行指令序列的处理器包括：状态保持单元，用于当执行预定指令时，保持所述预定指令的执行结果的更新状态; 获取单元，用于获得指令序列，所述指令序列由与分配给所述处理器的指令集的指令相匹配的指令组合，其中所述指令集被分配了第一条件指令;第一条件指令的第一状态条件与第二状态条件相互排斥，第二条件指令，其具有与第一条件指令相同的操作码，指令集不被分配第二条件指令，以及指定一个状态和多个状态中的一个状态和多个状态的第一状态条件和第二状态条件; 解码单元，用于逐个地解码所获得的指令序列中的每个指令; 判断单元，用于当解码单元解码第一条件指令时，判断更新状态是否包括在第一条件指令中由第一状态条件指定的状态和多个状态中的任一状态; 以及执行单元，用于仅当判断单元的判断结果为肯定时，执行由解码单元解码的第一条件指令中由操作码指定的操作。

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