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31. 发明申请

US20060031661A1 Processor for executing instructions in units that are unrelated to the units in wihcih instructions are read,and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor 有权
标题翻译：读取用于以与wihcih指令中的单元无关的单元执行指令的处理器，以及用于这种处理器的编译器，优化装置，汇编器，链接器，调试器和反汇编器
公开(公告)号：US20060031661A1
公开(公告)日：2006-02-09
申请号：US11245357
申请日：2005-10-07
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/40
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a-409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a-409c解码分支指令时，包括在分支指令中的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

32. 发明授权

US06904135B2 Compound device and telephone station device connected to the same, and power supply system and portable telephone system using compound device 失效
标题翻译：复合设备和电话站设备连接在一起，电源系统和便携式电话系统使用复合设备
公开(公告)号：US06904135B2
公开(公告)日：2005-06-07
申请号：US10172216
申请日：2002-06-14
申请人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
发明人： Shuichi Takayama , Nobuo Higaki , Hajime Ogawa , Taketo Heishi
IPC分类号： H04B1/38 , H04B7/26 , H04M1/00 , H04M1/723 , H04M1/725 , H04N5/44 , H04W4/24 , H04W76/02 , H04W88/02 , H04W88/08 , H04W88/14 , H04M11/00 , H04B1/00
CPC分类号： H04B1/005 , H04B1/3805 , H04M1/725 , H04N5/4401 , H04N21/2408 , H04N21/2543 , H04N21/4126 , H04N21/4263 , H04N21/42676 , H04N21/433 , H04N21/43637 , H04N21/44227 , H04N21/443 , H04N21/6112 , H04N21/6162 , H04N21/6168 , H04N21/654 , H04N21/6582 , H04N21/6583
摘要： A compound device has the structural hardware of a digital television, is connected to an antenna and a telephone station, and by reading out and running either a digital television (DTV) program or a base station program with a general processor, it has both the function of a digital television and the function of a portable telephone base station. The owner of the compound device receives discounts in their subscribed telephone fee or their power fee based on records in a communication record portion. Thus, a compound device in which a digital television is given the function of a portable telephone base station is provided, so that a novel infrastructure can be achieved in which insufficiencies in base stations are made up for without requiring equipment investment expenditures and portable device owners are given financial benefits in compensation for allowing the public use of their private possession as a portable telephone base station.
摘要翻译：复合设备具有数字电视的结构硬件，连接到天线和电话台，并且通过读取和运行数字电视（DTV）程序或使用通用处理器的基站程序，它具有数字电视的功能和便携式电话基站的功能。复合设备的所有者根据通信记录部分中的记录，收到其订阅的电话费或其电费的折扣。因此，提供了数字电视机被赋予便携式电话基站的功能的复合装置，从而可以实现基站的不足之处，不需要设备投资支出和便携式设备所有者的新颖的基础设施给予经济利益，允许公共使用私人拥有作为便携式电话基站。

33. 发明授权

US07761692B2 Processor, compiler and compilation method 有权
标题翻译：处理器，编译器和编译方法
公开(公告)号：US07761692B2
公开(公告)日：2010-07-20
申请号：US11452282
申请日：2006-06-14
申请人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
发明人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F9/3853 , G06F9/30072 , G06F9/3822
摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.
摘要翻译：为了克服有条件执行的指令如果不满足条件而被执行为无操作指令的问题，导致硬件的利用效率差并且降低了有效性能，则处理器解码大于提供的计算单元的数量并且在执行阶段之前用指令发布控制部分判断其执行条件，条件为假的指令被无效，并且分配后续的有效指令，使得有效地使用计算单元（硬件）。编译器执行调度，使得执行条件为真的指令数量不超过硬件的并行度的上限。在每个周期上平行布置的指令数可能超过硬件的并行程度。

34. 发明授权

US07594099B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07594099B2
公开(公告)日：2009-09-22
申请号：US11896368
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/305
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC0〜VC3（110）全部为零，并且（i）设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时，分别将条件标志寄存器（CFR）32至1和0分别设置为条件标志寄存器（CFR）32和C5，以及（ii）分别将条件标志C4和C5设置为0和1，并非所有向量条件标志都为零。然后，矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。

35. 发明申请

US20080046704A1 Processor executing SIMD instructions 审中-公开
标题翻译：处理器执行SIMD指令
公开(公告)号：US20080046704A1
公开(公告)日：2008-02-21
申请号：US11896371
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/38
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

36. 发明申请

US20060242387A1 Processor, compiler and compilation method 有权
公开(公告)号：US20060242387A1
公开(公告)日：2006-10-26
申请号：US11452282
申请日：2006-06-14
申请人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
发明人： Taketo Heishi , Shuichi Takayama , Tetsuya Tanaka , Hajime Ogawa , Nobuo Higaki
IPC分类号： G06F9/44
CPC分类号： G06F9/3853 , G06F9/30072 , G06F9/3822
摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

37. 发明授权

US06976245B2 PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR 有权
标题翻译：执行单元中指令的处理程序，与指令读取的单元相关，以及编译器，优化设备，汇编器，链接器，调试器和此类处理器的分解器
公开(公告)号：US06976245B2
公开(公告)日：2005-12-13
申请号：US10012725
申请日：2001-10-22
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G09F9/44
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

38. 发明授权

US08151254B2 Compiler, compiler apparatus and compilation method 有权
标题翻译：编译器，编译器和编译方法
公开(公告)号：US08151254B2
公开(公告)日：2012-04-03
申请号：US11790215
申请日：2007-04-24
申请人： Taketo Heishi , Toshiyuki Sakata , Hajime Ogawa , Ryoko Miyachi , Shuji Miyasaka , Tomokazu Ishikawa
发明人： Taketo Heishi , Toshiyuki Sakata , Hajime Ogawa , Ryoko Miyachi , Shuji Miyasaka , Tomokazu Ishikawa
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/425 , G06F8/427 , G06F8/4441
摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.
摘要翻译：提供包括在源程序101中的操作者定义文件102等以及将源程序101转换为机器语言程序105的编译器100。操作者定义文件102包括通过类定义的各种定点类型操作符的定义。编译器100可以生成有效的高级特定指令，处理器执行并通过扩展功能等进行改进，而不会重复频繁升级编译器本身的版本。编译器100由生成中间代码的中间代码生成单元121构成，机器语言指令替换单元122，其使用机器语言指令代替参考由操作者定义文件102定义的类别的中间代码和优化单元130，执行针对包括替代机器语言指令的中间代码的优化。

39. 发明授权

US07386844B2 Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions 有权
标题翻译：通过减少两个指令之间的汉明距离来优化源程序的编译器装置和方法
公开(公告)号：US07386844B2
公开(公告)日：2008-06-10
申请号：US10760429
申请日：2004-01-21
申请人： Taketo Heishi , Hajime Ogawa , Takenobu Tani , Yukihiro Sasagawa
发明人： Taketo Heishi , Hajime Ogawa , Takenobu Tani , Yukihiro Sasagawa
IPC分类号： G06F9/45 , G06F1/00 , G06F1/26
CPC分类号： G06F9/3001 , G06F8/4432 , G06F9/30156 , G06F9/3836 , G06F9/3838 , Y02D10/41
摘要： A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.
摘要翻译：编译装置能够产生指令序列，使得处理器以更低的功耗进行操作。编译装置将源程序转换为用于处理器的机器语言程序，所述处理器包括可并行执行指令的执行单元，并且包括执行单元分别执行执行指令的指令发布单元。编译器装置包括可解析源程序的解析器单元，可操作以将解析的源程序转换为中间代码的中间代码转换单元，可优化中间代码以减少来自相同指令的指令之间的汉明距离的优化单元发布单元，并且包括可以将优化的中间代码转换成机器语言指令的代码生成单元。

40. 发明申请

US20080046690A1 Processor executing SIMD instructions 审中-公开
公开(公告)号：US20080046690A1
公开(公告)日：2008-02-21
申请号：US11896370
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

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