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1. 发明申请

US20080046687A1 Processor executing SIMD instructions 有权
公开(公告)号：US20080046687A1
公开(公告)日：2008-02-21
申请号：US11896368
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302 , G06F15/80
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

2. 发明授权

US07594099B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07594099B2
公开(公告)日：2009-09-22
申请号：US11896368
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/305
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC0〜VC3（110）全部为零，并且（i）设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时，分别将条件标志寄存器（CFR）32至1和0分别设置为条件标志寄存器（CFR）32和C5，以及（ii）分别将条件标志C4和C5设置为0和1，并非所有向量条件标志都为零。然后，矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。

3. 发明申请

US20080046704A1 Processor executing SIMD instructions 审中-公开
标题翻译：处理器执行SIMD指令
公开(公告)号：US20080046704A1
公开(公告)日：2008-02-21
申请号：US11896371
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/38
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

4. 发明申请

US20080046688A1 Processor executing SIMD instructions 审中-公开
标题翻译：处理器执行SIMD指令
公开(公告)号：US20080046688A1
公开(公告)日：2008-02-21
申请号：US11896369
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F15/80 , G06F9/315
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

5. 发明授权

US07281117B2 Processor executing SIMD instructions 有权
标题翻译：处理器执行SIMD指令
公开(公告)号：US07281117B2
公开(公告)日：2007-10-09
申请号：US10668358
申请日：2003-09-24
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302 , G06F9/318
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译：根据本发明的处理器包括解码单元20，操作单元40等。当解码单元20解码指令vcchk时，操作单元40等判断条件标志寄存器（CFR）32的矢量条件标志VC 0〜VC 3（110）是否全部为零，以及（i）设置条件当所有向量条件标志VC 0〜VC 3都为零时，分别为条件标志寄存器（CFR）32〜1和0的标志C 4和C 5，（ii）设定条件标志C 4和C 5 分别为0和1，当不是全部矢量条件标志为零时。然后，矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。

6. 发明申请

US20080046690A1 Processor executing SIMD instructions 审中-公开
公开(公告)号：US20080046690A1
公开(公告)日：2008-02-21
申请号：US11896370
申请日：2007-08-31
申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号： G06F9/302
CPC分类号： G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

7. 发明授权

US07395410B2 Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor 有权
标题翻译：处理器系统具有改进的指令解码控制单元，用于控制处理器和协处理器之间的数据传输
公开(公告)号：US07395410B2
公开(公告)日：2008-07-01
申请号：US11172601
申请日：2005-06-30
申请人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
发明人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
IPC分类号： G06F15/16
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.
摘要翻译：处理器系统包括具有寄存器和指令解码控制单元的主处理器以及协处理器。当主处理器根据指令执行操作时，寄存器存储要用于操作的数据和通过操作获得的数据，并且控制单元顺序地解码指令，并且基于该指令进行控制。当解码协处理器操作指令以请求协处理器执行操作时，其包括指定要由协处理器执行的操作的类型的操作数，存储要用于操作的数据的第一寄存器和用于存储数据的第二寄存器通过该操作获得，控制单元通过使用第一寄存器中的内容来请求协处理器执行指定类型的操作，并且使第二寄存器存储操作的结果。

8. 发明申请

US20060010305A1 Processor system that controls data transfer between processor and coprocessor 有权
标题翻译：控制处理器和协处理器之间数据传输的处理器系统
公开(公告)号：US20060010305A1
公开(公告)日：2006-01-12
申请号：US11172601
申请日：2005-06-30
申请人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
发明人： Masaki Maeda , Hiroyuki Morishita , Takeshi Tanaka , Tokuzo Kiyohara
IPC分类号： G06F15/00
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.
摘要翻译：处理器系统包括具有寄存器和指令解码控制单元的主处理器以及协处理器。当主处理器根据指令执行操作时，寄存器存储要用于操作的数据和通过操作获得的数据，并且控制单元顺序地解码指令，并且基于该指令进行控制。当解码协处理器操作指令以请求协处理器执行操作时，其包括指定要由协处理器执行的操作的类型的操作数，存储要用于操作的数据的第一寄存器和用于存储数据的第二寄存器通过该操作获得，控制单元通过使用第一寄存器中的内容来请求协处理器执行指定类型的操作，并且使第二寄存器存储操作的结果。

9. 发明申请

US20120154414A1 INTEGRATED CIRCUIT FOR USE IN PLASMA DISPLAY PANEL, ACCESS CONTROL METHOD, AND PLASMA DISPLAY SYSTEM 有权
标题翻译：用于等离子显示面板的集成电路，访问控制方法和等离子体显示系统
公开(公告)号：US20120154414A1
公开(公告)日：2012-06-21
申请号：US13393349
申请日：2011-06-09
申请人： Masaki Maeda , Naoki Ootani , Tokuzo Kiyohara
发明人： Masaki Maeda , Naoki Ootani , Tokuzo Kiyohara
IPC分类号： G09G3/28 , G06F13/372 , G09G5/39
CPC分类号： G09G3/288 , G09G3/2022 , G09G3/293 , G09G5/395 , G09G2320/103
摘要： Provided is a plasma display system capable of restricting peak data traffic when a shared memory is used. In the plasma display system, a control unit 104 prohibits a moving picture decoder 101 from accessing a shared memory 140 while an SF reading unit 101 is reading, from the shared memory 140, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit 104 permits the moving picture decoder 101 to access the shared memory 140 while the SF reading unit 101 is not reading the SF pixel data from the shared memory 140, that is to say, during a sustain discharge period.
摘要翻译：提供了当使用共享存储器时能够限制峰值数据业务的等离子体显示系统。在等离子体显示系统中，控制单元104在SF读取单元101从共享存储器140读取作为要点燃的各个单元的信息的SF像素数据的同时，禁止运动图像解码器101访问共享存储器140 多个子场。另一方面，控制单元104允许运动图像解码器101访问共享存储器140，而SF读取单元101不从共享存储器140读取SF像素数据，即在维持放电期间。

10. 发明授权

US09189989B2 Integrated circuit for use in plasma display panel, access control method, and plasma display system 有权
标题翻译：用于等离子体显示面板的集成电路，门禁控制方法和等离子体显示系统
公开(公告)号：US09189989B2
公开(公告)日：2015-11-17
申请号：US13393349
申请日：2011-06-09
申请人： Masaki Maeda , Naoki Ootani , Tokuzo Kiyohara
发明人： Masaki Maeda , Naoki Ootani , Tokuzo Kiyohara
IPC分类号： G09G3/28 , G09G3/288 , G09G3/293 , G09G3/20 , G09G5/395
CPC分类号： G09G3/288 , G09G3/2022 , G09G3/293 , G09G5/395 , G09G2320/103
摘要： A plasma display system restricts peak data traffic when a shared memory is used. In the plasma display system, a control unit prohibits a moving picture decoder from accessing a shared memory while an SF reading unit is reading, from the shared memory, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit permits the moving picture decoder to access the shared memory while the SF reading unit is not reading the SF pixel data from the shared memory during a sustain discharge period.
摘要翻译：当使用共享存储器时，等离子体显示系统限制峰值数据流量。在等离子体显示系统中，控制单元在SF读取单元正在从共享存储器读取作为多个子场中要照明的单元的信息的SF像素数据时，禁止运动图像解码器访问共享存储器。另一方面，控制单元允许运动图像解码器访问共享存储器，而SF读取单元在维持放电期间未从共享存储器读取SF像素数据。

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