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31. 发明申请

US20120286266A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120286266A1
公开(公告)日：2012-11-15
申请号：US13555579
申请日：2012-07-23
申请人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA , Shunichi ITO , Miyuki HOSOBA
发明人： Hideomi SUZAWA , Shinya SASAGAWA , Taiga MURAOKA , Shunichi ITO , Miyuki HOSOBA
IPC分类号： H01L29/26
CPC分类号： H01L29/66969 , H01L27/1225 , H01L27/1288 , H01L29/66742 , H01L29/78621 , H01L29/7869
摘要： An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
摘要翻译：本发明的目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。在包括通道蚀刻的半导体器件的制造方法中倒置交错薄膜晶体管，氧化物半导体膜和导电膜使用掩模层进行蚀刻，该掩模层使用作为透光的多色调掩模形成，该透光掩模通过该曝光掩模透射，以便具有多个强度在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。

32. 发明申请

US20120270375A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20120270375A1
公开(公告)日：2012-10-25
申请号：US13446022
申请日：2012-04-13
申请人： Shinya SASAGAWA , Akihiro ISHIZUKA
发明人： Shinya SASAGAWA , Akihiro ISHIZUKA
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/42384 , H01L29/785 , H01L29/78603 , H01L29/7869 , H01L29/78696
摘要： To provide a semiconductor device which prevents defects and achieves miniaturization. A projecting portion or a trench (a groove portion) is formed in an insulating layer and a channel formation region of a semiconductor layer is provided in contact with the projecting portion or the trench, so that the channel formation region is extended in a direction perpendicular to a substrate. Thus, miniaturization of the transistor can be achieved and an effective channel length can be extended. In addition, before formation of the semiconductor layer, an upper-end corner portion of the projecting portion or the trench with which the semiconductor layer is in contact is subjected to round chamfering, so that a thin semiconductor layer can be formed with good coverage.
摘要翻译：提供一种防止缺陷并实现小型化的半导体器件。在绝缘层中形成突出部分或沟槽（沟槽部分），并且半导体层的沟道形成区域设置成与突出部分或沟槽接触，使得沟道形成区域在垂直方向上延伸到基底。因此，可以实现晶体管的小型化并且可以延长有效的沟道长度。此外，在形成半导体层之前，突出部分的上端拐角部分或与半导体层接触的沟槽进行圆形倒角，从而可以形成具有良好覆盖的薄半导体层。

33. 发明申请

US20120267624A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120267624A1
公开(公告)日：2012-10-25
申请号：US13446028
申请日：2012-04-13
申请人： Atsuo ISOBE , Toshinari SASAKI , Shinya SASAGAWA , Akihiro ISHIZUKA
发明人： Atsuo ISOBE , Toshinari SASAKI , Shinya SASAGAWA , Akihiro ISHIZUKA
IPC分类号： H01L29/24 , H01L21/34
CPC分类号： H01L29/66969 , H01L21/02554 , H01L21/02565 , H01L21/02667 , H01L27/0688 , H01L27/1225 , H01L29/42384 , H01L29/78603 , H01L29/78642 , H01L29/7869 , H01L29/78696
摘要： An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.
摘要翻译：绝缘层设置有突出的结构体，并且设置与突出结构体接触的氧化物半导体层的沟道形成区域，由此沟道形成区域沿三维方向（垂直于衬底的方向）延伸）。因此，可以使晶体管小型化并且延长晶体管的有效沟道长度。此外，突出结构体的顶表面和侧表面彼此相交的突出结构体的上端角部弯曲，并且氧化物半导体层形成为包括具有c轴的晶体垂直于曲面。

34. 发明申请

US20120187397A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120187397A1
公开(公告)日：2012-07-26
申请号：US13356012
申请日：2012-01-23
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Toshihiko SAITO , Takehisa HATANO , Hideomi SUZAWA , Shinya SASAGAWA , Junichi KOEZUKA , Yuichi SATO , Shinji OHNO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Toshihiko SAITO , Takehisa HATANO , Hideomi SUZAWA , Shinya SASAGAWA , Junichi KOEZUKA , Yuichi SATO , Shinji OHNO
IPC分类号： H01L29/786
CPC分类号： H01L29/66969 , H01L21/02488 , H01L21/02565 , H01L27/1225 , H01L29/786 , H01L29/78606 , H01L29/7869
摘要： A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
摘要翻译：提供了包括氧化物半导体并且具有良好的电特性的半导体器件。在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。氧化物半导体膜的侧面与绝缘膜接触。氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。栅极绝缘膜与氧化物半导体膜形成并接触。在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。

35. 发明申请

US20110250723A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20110250723A1
公开(公告)日：2011-10-13
申请号：US13078020
申请日：2011-04-01
申请人： Hideomi SUZAWA , Shinya SASAGAWA
发明人： Hideomi SUZAWA , Shinya SASAGAWA
IPC分类号： H01L21/336
CPC分类号： H01L29/78636 , G11C16/0433 , H01L27/0688 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/7869
摘要： In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.
摘要翻译：在一个实施例中，在平坦表面上形成绝缘膜; 在绝缘膜上形成掩模; 在面罩上进行减肥过程; 使用掩模对绝缘膜进行蚀刻处理; 形成覆盖绝缘膜的导电膜; 对导电膜和绝缘膜进行抛光处理，使得导电膜和绝缘膜具有相等的厚度; 蚀刻导电膜，形成比导电膜薄的源电极和漏电极; 形成与绝缘膜，源电极和漏电极接触的氧化物半导体膜; 形成覆盖氧化物半导体膜的栅极绝缘膜; 并且栅电极形成在栅极绝缘膜上并与绝缘膜重叠的区域中。

36. 发明申请

US20110207269A1 TRANSISTOR AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20110207269A1
公开(公告)日：2011-08-25
申请号：US13026520
申请日：2011-02-14
申请人： Shinya SASAGAWA , Masashi TSUBUKU , Hitoshi NAKAYAMA , Daigo SHIMADA
发明人： Shinya SASAGAWA , Masashi TSUBUKU , Hitoshi NAKAYAMA , Daigo SHIMADA
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/32136 , H01L21/32139 , H01L29/66969 , H01L29/7869
摘要： A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.
摘要翻译：晶体管通过以下方法制造：包括：形成第一布线层; 形成第一绝缘膜以覆盖所述第一布线层; 在所述第一绝缘膜上形成半导体层; 在半导体层上形成导电膜; 并且对所述导电膜进行蚀刻的至少两个步骤以形成彼此分离的第二布线层，其中所述两个蚀刻步骤至少包括在导电膜的蚀刻速率为高于半导体层的蚀刻速率，以及在导电膜和半导体层的蚀刻速率高于第一蚀刻工艺的蚀刻速率的条件下进行的第二蚀刻工艺。

37. 发明申请

US20110180796A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110180796A1
公开(公告)日：2011-07-28
申请号：US13008285
申请日：2011-01-18
申请人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
发明人： Shunpei YAMAZAKI , Hiromichi GODO , Hideomi SUZAWA , Shinya SASAGAWA , Motomu KURATA , Mayumi MIKAMI
IPC分类号： H01L29/24
CPC分类号： H01L29/7869
摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.
摘要翻译：本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层，其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

38. 发明申请

US20100062556A1 METHODS FOR MANUFACTURING THIN FILM TRANSISTOR AND DISPLAY DEVICE 有权
标题翻译：制造薄膜晶体管和显示器件的方法
公开(公告)号：US20100062556A1
公开(公告)日：2010-03-11
申请号：US12545276
申请日：2009-08-21
申请人： Shinya SASAGAWA , Akihiro ISHIZUKA , Shigeki KOMORI
发明人： Shinya SASAGAWA , Akihiro ISHIZUKA , Shigeki KOMORI
IPC分类号： H01L33/00 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1255 , H01L29/04 , H01L29/41733 , H01L29/66765 , H01L29/78696
摘要： The present invention provides a method for manufacturing a thin film transistor with small leakage current and high switching characteristics. In a method for manufacturing a thin film transistor, a back channel portion is formed in the thin film transistor by conducting etching using a resist mask, the resist mask is removed by removal or the like, and a superficial part of the back channel portion is further etched. Through the steps, components of chemical solution used for the removal, residues of the resist mask, and the like which exist at the superficial part of the back channel portion can be removed and leakage current can be reduced. The further etching step of the back channel portion is preferably conducted by dry etching using an N2 gas or a CF4 gas with bias not applied.
摘要翻译：本发明提供一种制造漏电流小，开关特性高的薄膜晶体管的制造方法。在制造薄膜晶体管的方法中，通过使用抗蚀剂掩模进行蚀刻，在薄膜晶体管中形成背沟道部分，通过去除等除去抗蚀剂掩模，并且背沟道部分的表面部分是进一步刻蚀。通过这些步骤，可以去除存在于背部通道部分的表面部分的用于去除的化学溶液的组分，抗蚀剂掩模的残留物等，并且可以减少泄漏电流。后通道部分的进一步蚀刻步骤优选通过使用N 2气体或没有施加偏压的CF 4气体进行干蚀刻来进行。

39. 发明申请

US20090206494A1 WIRING OVER SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING THEREOF 有权
标题翻译：基板接线，半导体器件及其制造方法
公开(公告)号：US20090206494A1
公开(公告)日：2009-08-20
申请号：US12431170
申请日：2009-04-28
申请人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
发明人： Shinya SASAGAWA , Satoru OKAMOTO , Shigeharu MONOE
IPC分类号： H01L23/52 , C23F1/00 , H01L21/3205 , H05K1/00
CPC分类号： H01L27/3276 , G02F2001/13629 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L51/0021 , H01L51/0023 , H01L51/5281 , H01L2924/0002 , H05K3/06 , H05K2203/0315 , H05K2203/0346 , H05K2203/095 , H05K2203/1476 , H01L2924/00
摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.
摘要翻译：公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于第一个条件。

40. 发明申请

US20090111248A1 MANUFACTURING METHOD OF SOI SUBSTRATE 有权
标题翻译： SOI衬底的制造方法
公开(公告)号：US20090111248A1
公开(公告)日：2009-04-30
申请号：US12247487
申请日：2008-10-08
申请人： Hideto OHNUMA , Tetsuya KAKEHATA , Akihisa SHIMOMURA , Shinya SASAGAWA , Motomu KURATA
发明人： Hideto OHNUMA , Tetsuya KAKEHATA , Akihisa SHIMOMURA , Shinya SASAGAWA , Motomu KURATA
IPC分类号： H01L21/02
CPC分类号： H01L21/76254 , H01L21/02532 , H01L21/02686 , H01L21/268 , H01L21/302 , H01L21/3065 , H01L21/84
摘要： A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the single crystal semiconductor layer.
摘要翻译：通过源气体的激发产生等离子体并通过从单晶半导体衬底的表面之一添加包含在等离子体中的离子种类而形成损伤区域; 在单晶半导体衬底的另一个表面上形成绝缘层; 支撑衬底牢固地附接到单晶半导体衬底，以便在其间插入绝缘层的单晶半导体衬底; 通过加热单晶半导体衬底，在损伤区域处分离成与单晶半导体层相连的支撑衬底和部分单晶半导体衬底; 在附着于支撑基板的单晶半导体层的表面进行干蚀刻，通过用激光束照射单晶半导体层来使单晶半导体层重结晶，从而熔化至少一部分单晶半导体层。

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