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31. 发明授权

US07002384B1 Loop circuitry with low-pass noise filter 失效
标题翻译：具有低通噪声滤波器的回路电路
公开(公告)号：US07002384B1
公开(公告)日：2006-02-21
申请号：US10759915
申请日：2004-01-16
申请人： Yan Chong , Joseph Huang , Chiakang Sung , Philip Pan , Tzung-chin Chang
发明人： Yan Chong , Joseph Huang , Chiakang Sung , Philip Pan , Tzung-chin Chang
IPC分类号： H03K5/13 , H03D3/24
CPC分类号： H03L7/0814 , H03L7/085 , H03L7/093
摘要： Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.
摘要翻译：提供了用于环路电路（即DLL电路和PLL电路）的相位比较器。相位比较器包括用于比较参考时钟信号和从产生的环路电路生成的内部时钟信号导出的反馈信号的相位检测器。相位比较器还包括低通噪声滤波器，用于通过在环路电路的补偿电路之前需要一定的净数量的前导或滞后检测来滤除参考时钟信号和反馈信号之间的错误检测的相位差（即，调节DLL电路中的受控延迟线或PLL电路中的受控振荡器）。在进行这些调整之前所需的净测量数取决于提供给相位比较器的可编程带宽信号。

32. 发明授权

US06853215B1 Programmable I/O element circuit for high speed logic devices 失效
标题翻译：用于高速逻辑器件的可编程I / O元件电路
公开(公告)号：US06853215B1
公开(公告)日：2005-02-08
申请号：US10685355
申请日：2003-10-09
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
IPC分类号： C07K14/47 , C07K16/28 , H03K19/173
CPC分类号： C07K16/28 , A61K2039/505 , C07K14/47
摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.
摘要翻译：用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速110模式（例如双数据速率和零总线周转）进行操作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

33. 发明授权

US06806733B1 Multiple data rate interface architecture 有权
标题翻译：多数据速率接口架构
公开(公告)号：US06806733B1
公开(公告)日：2004-10-19
申请号：US10038737
申请日：2002-01-02
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H03K19177
CPC分类号： H03K19/1774 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

34. 发明授权

US06766505B1 Parallel programming of programmable logic using register chains 有权
标题翻译：使用寄存器链的可编程逻辑的并行编程
公开(公告)号：US06766505B1
公开(公告)日：2004-07-20
申请号：US10106675
申请日：2002-03-25
申请人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
发明人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
IPC分类号： G06F1750
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17764 , Y02T10/82
摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register includes two or more serial register chains, each chain being made up of a serial chain of registers. The configuration data is input into the two of more chains of the data registers in parallel. Circuitry is also provided to handle redundancy.
摘要翻译：技术和电路用于更快速地配置可编程集成电路。配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。配置数据将被存储在数据寄存器（722）中。该数据寄存器包括两个或多个串行寄存器链，每个链由串行寄存器组成。配置数据并行输入数据寄存器的两个链中。还提供电路来处理冗余。

35. 发明授权

US08779754B2 Method and apparatus for minimizing skew between signals 有权
标题翻译：用于最小化信号之间的偏差的方法和装置
公开(公告)号：US08779754B2
公开(公告)日：2014-07-15
申请号：US13019277
申请日：2011-02-01
申请人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
发明人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
IPC分类号： H03K5/14 , H03K5/13 , H03K5/15
CPC分类号： H03K5/135 , G01R31/3016 , G01R31/31725 , G01R31/318516 , H03K5/14 , H03K5/1504
摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
摘要翻译：使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。两个信号之间的偏差被量化为测量延迟的差。在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

36. 发明授权

US08159277B1 Techniques for providing multiple delay paths in a delay circuit 有权
标题翻译：在延迟电路中提供多个延迟路径的技术
公开(公告)号：US08159277B1
公开(公告)日：2012-04-17
申请号：US13031129
申请日：2011-02-18
申请人： Pradeep Nagarajan , Yan Chong , Chiakang Sung , Joseph Huang
发明人： Pradeep Nagarajan , Yan Chong , Chiakang Sung , Joseph Huang
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058
摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.
摘要翻译：反馈回路包括相位检测器和延迟电路。相位检测器基于延迟周期信号产生输出信号。延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。

37. 发明授权

US08098082B1 Multiple data rate interface architecture 有权
标题翻译：多数据速率接口架构
公开(公告)号：US08098082B1
公开(公告)日：2012-01-17
申请号：US12954204
申请日：2010-11-24
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

38. 发明授权

US07884619B1 Method and apparatus for minimizing skew between signals 有权
标题翻译：用于最小化信号之间的偏差的方法和装置
公开(公告)号：US07884619B1
公开(公告)日：2011-02-08
申请号：US12566157
申请日：2009-09-24
申请人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
发明人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
IPC分类号： G01R35/00 , G01R23/175 , G08B23/00 , H03L7/00
CPC分类号： H03K5/135 , G01R31/3016 , G01R31/31725 , G01R31/318516 , H03K5/14 , H03K5/1504
摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
摘要翻译：使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。两个信号之间的偏差被量化为测量延迟的差。在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

39. 发明授权

US07859304B1 Multiple data rate interface architecture 有权
标题翻译：多数据速率接口架构
公开(公告)号：US07859304B1
公开(公告)日：2010-12-28
申请号：US12329553
申请日：2008-12-06
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

40. 发明授权

US07593273B2 Read-leveling implementations for DDR3 applications on an FPGA 有权
标题翻译： FPGA上DDR3应用程序的读取级别实现
公开(公告)号：US07593273B2
公开(公告)日：2009-09-22
申请号：US11935310
申请日：2007-11-05
申请人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译：用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。一个例子是通过在输入和电路之间使用重新定时元件实现这一点。重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。平均接收无差错数据的最小和最大延迟。然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。在一个示例中，输入信号可以被延迟与延迟设置相对应的量。在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

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