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31. 发明申请

US20050285188A1 LDMOS transistor 有权
标题翻译： LDMOS晶体管
公开(公告)号：US20050285188A1
公开(公告)日：2005-12-29
申请号：US10875105
申请日：2004-06-23
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/06 , H01L29/47 , H01L29/76 , H01L29/78
CPC分类号： H01L29/782 , H01L27/0727 , H01L29/0619 , H01L29/0653 , H01L29/47 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.
摘要翻译： LDMOS晶体管具有插入在LDMOS晶体管的掺杂区域的中心处的肖特基二极管。典型的LDMOS晶体管在中心具有漂移区域。在这种情况下，肖特基二极管插在该漂移区的中心，其具有提供从正向连接到源极到漏极的肖特基二极管的作用，使得漏极电压被钳位到低于PN结的电压阈值，从而避免正向偏置PN结。一种替代方案是将肖特基二极管插入其中形成源的阱，其位于LDMOS晶体管的外围。在这种情况下，肖特基二极管的形成方式不同，但仍然在正向方向上从源极到漏极连接，以在漏极处实现所需的电压钳位。

32. 发明申请

US20050275055A1 Schottky device 失效
标题翻译：肖特基装置
公开(公告)号：US20050275055A1
公开(公告)日：2005-12-15
申请号：US10856602
申请日：2004-05-28
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/06 , H01L27/07 , H03K19/00
CPC分类号： H01L27/0727 , H01L27/0629
摘要： A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.
摘要翻译：正交肖特基二极管或具有肖特基二极管特性和MOS晶体管的器件串联耦合以提供泄漏电流和击穿电压的显着改进，只有正向电流的降低很小。在反向偏置情况下，存在小的反向偏置电流，但由于MOS晶体管，肖特基二极管两端的电压保持较小。几乎所有的反向偏置电压都跨越MOS晶体管，直到MOS晶体管故障。然而，该晶体管击穿不是最初的破坏性，因为肖特基二极管限制了电流。随着反向偏压持续增加，肖特基二极管开始吸收更多的电压。这增加了漏电流，但是在晶体管和肖特基二极管之间的击穿电压稍微相加。

33. 发明授权

US06815780B1 Semiconductor component with substrate injection protection structure 有权
标题翻译：半导体元件具有基板注入保护结构
公开(公告)号：US06815780B1
公开(公告)日：2004-11-09
申请号：US10417972
申请日：2003-04-15
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L2976
CPC分类号： H01L21/76224 , H01L21/763
摘要： A semiconductor component includes a semiconductor substrate (210) having a first conductivity type, a semiconductor epitaxial layer (220) having the first conductivity type located over the semiconductor substrate, a first semiconductor device (110) and a second semiconductor device (130) located in the semiconductor epitaxial layer and including, respectively, a first semiconductor region (120) and a second semiconductor region (140), both having the second conductivity type, an ohmic contact region (150) in the semiconductor epitaxial layer having the first conductivity type and located between the first and second semiconductor devices, and at least one electrically insulating trench (160, 360) located in the semiconductor epitaxial layer and circumscribing at least the first semiconductor device. The semiconductor epitaxial layer has a doping concentration lower than a doping concentration of the semiconductor substrate.

34. 发明授权

US06734524B1 Electronic component and method of manufacturing same 有权
标题翻译：电子元件及其制造方法
公开(公告)号：US06734524B1
公开(公告)日：2004-05-11
申请号：US10335030
申请日：2002-12-31
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose , Todd Roggenbauer , Paul Hui
IPC分类号： H01L2900
CPC分类号： H01L27/088 , H01L21/76232
摘要： An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.
摘要翻译：电子部件包括半导体衬底（110），半导体衬底上的外延半导体层（120,221,222）以及外延半导体层中的半导体区域（130,230）。外延半导体层具有上表面（123）。外延半导体层的第一部分（121）位于半导体区域的下方，并且外延半导体层的第二部分（122）位于半导体区域的上方。半导体衬底和外延半导体层的第一部分具有第一导电类型，并且半导体区域具有第二导电类型。至少一个电绝缘沟槽（140,240）从外延半导体层的上表面延伸到半导体区域的至少一部分。半导体衬底的掺杂浓度高于外延半导体层的第一部分的掺杂浓度。

35. 发明授权

US08963241B1 Integrated MOS power transistor with poly field plate extension for depletion assist 有权
标题翻译：集成MOS功率晶体管，具有多场扩展功能，用于耗尽辅助
公开(公告)号：US08963241B1
公开(公告)日：2015-02-24
申请号：US13460717
申请日：2012-04-30
申请人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
发明人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0653 , H01L29/0619 , H01L29/0634 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/402 , H01L29/4238 , H01L29/7835
摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate and a polysilicon field plate. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more polysilicon extension tabs extend from the field plate to at least above the edge of the first doped region. The polysilicon gate is cut to form a cut-out region for the end of each polysilicon extension tab extending toward the body substrate. The one or more polysilicon extension tabs force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
摘要翻译：分离栅极功率晶体管包括掺杂衬底，衬底上的栅氧化层，以及形成多晶硅栅极和多晶硅场板的栅极氧化物层上的分裂多晶硅层。两个多晶硅部分被间隙隔开。场板电耦合到分离栅功率晶体管的源极。一个或多个多晶硅延伸片从场板延伸到至少在第一掺杂区的边缘上方。多晶硅栅极被切割以形成朝向主体衬底延伸的每个多晶硅延伸片的端部的切出区域。一个或多个多晶硅延伸片将场板下面的过渡区域的部分强制为深度耗尽，从而防止在该区域中形成空穴反转层。

36. 发明授权

US08969958B1 Integrated MOS power transistor with body extension region for poly field plate depletion assist 有权
标题翻译：集成MOS功率晶体管，具有用于多场板耗尽辅助的主体延伸区域
公开(公告)号：US08969958B1
公开(公告)日：2015-03-03
申请号：US13460603
申请日：2012-04-30
申请人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
发明人： Vishnu Khemka , Ronghua Zhu , Tahir Arif Khan , Bernhard Heinrich Grote
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0653 , H01L29/1095 , H01L29/401 , H01L29/4238 , H01L29/66659 , H01L29/7835
摘要： A split gate power transistor includes a doped substrate, a gate oxide layer on the substrate, and a split polysilicon layer over the gate oxide layer, which forms a polysilicon gate positioned over a channel region and a first portion of a transition region and a polysilicon field plate positioned over a second portion of the transition region and a shallow trench isolation region. The two polysilicon portions are separated by a gap. The field plate is electrically coupled to a source of the split gate power transistor. One or more body extension regions, each having the same doping type as the body substrate, extend at least underneath the edge of the field plate adjacent to the gap. The body extension regions force the portion of the transition region underneath the field plate into deep-depletion, thereby preventing the formation of a hole inversion layer in this region.
摘要翻译：分离栅功率晶体管包括掺杂衬底，衬底上的栅极氧化物层和栅极氧化物层上的分离多晶硅层，其形成位于沟道区域上的多晶硅栅极和过渡区域的第一部分以及多晶硅位于过渡区域的第二部分上的场板和浅沟槽隔离区域。两个多晶硅部分被间隙隔开。场板电耦合到分离栅功率晶体管的源极。每个具有与主体基板相同的掺杂类型的一个或多个本体延伸区域至少延伸到邻近间隙的场板的边缘的下方。体延伸区域迫使场板下方的过渡区域的部分深度耗尽，从而防止在该区域中形成空穴反转层。

37. 发明授权

US08987818B1 Integrated MOS power transistor with thin gate oxide and low gate charge 有权
标题翻译：具有薄栅极氧化物和低栅极电荷的集成MOS功率晶体管
公开(公告)号：US08987818B1
公开(公告)日：2015-03-24
申请号：US13312827
申请日：2011-12-06
申请人： Joel Montgomery McGregor , Vishnu Khemka
发明人： Joel Montgomery McGregor , Vishnu Khemka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/402
摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition region of the substrate. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap, thereby forming a bridge having the same doping type as the substrate body. The field plate also extends over a field oxide filled trench formed in the substrate. The field plate is electrically coupled to a source of the split gate power transistor.
摘要翻译：分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，形成在衬底的表面上的栅氧化层，以及形成在栅极氧化物层上的分裂多晶硅层。多晶硅层被切割成两个电隔离部分，第一部分形成位于衬底的沟道区上的多晶硅栅极，以及形成在衬底的过渡区域的一部分上的多晶硅场板的第二部分。两个多晶硅部分被间隙隔开。将轻掺杂区域注入到间隙下方的衬底中，从而形成具有与衬底本体相同的掺杂类型的桥。场板还在形成在衬底中的场氧化物填充沟槽上延伸。场板电耦合到分离栅功率晶体管的源极。

38. 发明授权

US08946851B1 Integrated MOS power transistor with thin gate oxide and low gate charge 有权
标题翻译：具有薄栅极氧化物和低栅极电荷的集成MOS功率晶体管
公开(公告)号：US08946851B1
公开(公告)日：2015-02-03
申请号：US13446987
申请日：2012-04-13
申请人： Joel Montgomery McGregor , Vishnu Khemka
发明人： Joel Montgomery McGregor , Vishnu Khemka
IPC分类号： H01L23/58
CPC分类号： H01L29/7835 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/402
摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate having a first doped region and a second doped region of an opposite type as the first doped region, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region and a transition region of the substrate, and a second portion forming a polysilicon field plate formed entirely over a field oxide filled trench formed in the second doped region. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap and adjacent to the trench, thereby forming a fill region having the same doping type as the first doped region.
摘要翻译：分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，其具有作为第一掺杂区的相反类型的第一掺杂区和第二掺杂区，形成在衬底表面上的栅氧化层，在栅极氧化物层上形成分裂的多晶硅层。将多晶硅层切割成两个电隔离部分，形成位于衬底的沟道区域和过渡区域上方的多晶硅栅极的第一部分，以及形成在形成在场氧化物填充沟槽上的整个场中的多晶硅场板的第二部分第二掺杂区域。两个多晶硅部分被间隙隔开。将轻掺杂区域注入到间隙下方的衬底中并与沟槽相邻，由此形成具有与第一掺杂区域相同的掺杂类型的填充区域。

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