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31. 发明申请

US20060285387A1 Flash memory device with NAND architecture with reduced capacitive coupling effect 有权
标题翻译：具有NAND架构的闪存器件具有降低的电容耦合效应
公开(公告)号：US20060285387A1
公开(公告)日：2006-12-21
申请号：US11445491
申请日：2006-05-31
申请人： Rino Micheloni , Roberto Ravasio , Iiaria Motta
发明人： Rino Micheloni , Roberto Ravasio , Iiaria Motta
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/3409
摘要： A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.
摘要翻译： NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。恢复逻辑相对于超过读取参考值的极限值读取每个组，仅对至少一个单元的阈值电压未达到极限值的每个组进行编程，并响应于达到极限值而停止恢复至少一组这些组。

32. 发明申请

US20050050434A1 Method for performing error corrections of digital information codified as a symbol sequence 有权
标题翻译：用于执行编码为符号序列的数字信息的纠错的方法
公开(公告)号：US20050050434A1
公开(公告)日：2005-03-03
申请号：US10805168
申请日：2004-03-19
申请人： Massimiliano Lunelli , Rlno Micheloni , Roberto Ravasio , Alessia Marelli
发明人： Massimiliano Lunelli , Rlno Micheloni , Roberto Ravasio , Alessia Marelli
IPC分类号： H03M13/13 , H03M13/15 , H03M13/19 , H03M13/00 , H03M13/03
CPC分类号： H03M13/1575 , H03M13/13 , H03M13/15 , H03M13/19
摘要： A method for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, providing the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to the invention, the error code incorporated in the original sequence belongs to a non Boolean group.
摘要翻译：描述了对编码为符号序列的数字信息进行错误校正的方法，例如存储在电子存储器系统中或从这些系统发送的数字信息或从这些系统发送和传送到这些系统的数字信息，提供包含错误校正码的一部分的序列的传输，更可能的是，通过使用奇偶校验矩阵计算错误校正子来传送原始信息，以便在接收时恢复。有利的是，根据本发明，并入原始序列中的错误代码属于非布尔组。

33. 发明授权

US08966335B2 Method for performing error corrections of digital information codified as a symbol sequence 有权
标题翻译：用于执行编码为符号序列的数字信息的纠错的方法
公开(公告)号：US08966335B2
公开(公告)日：2015-02-24
申请号：US12001294
申请日：2007-12-10
申请人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
发明人： Massimiliano Lunelli , Rino Micheloni , Roberto Ravasio , Alessia Marelli
IPC分类号： H03M13/00 , H03M13/19 , H03M13/13 , H03M13/15
CPC分类号： H03M13/1575 , H03M13/13 , H03M13/15 , H03M13/19
摘要： A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.
摘要翻译：描述了一种用于对编码为符号序列的数字信息进行纠错的方法和系统，例如存储在电子存储器系统中或从这些系统发送的数字信息或从这些系统发送和传送到这些系统的数字信息，提供包含一部分误差校正码的序列的传输，这更可能是通过使用在接收时要恢复的奇偶校验矩阵的误差校正子的计算来传送的。有利地，根据本发明的实施例，并入原始序列中的错误代码属于非布尔组。

34. 发明授权

US08572361B2 Configuration of a multilevel flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US08572361B2
公开(公告)日：2013-10-29
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

35. 发明授权

US08347201B2 Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code 有权
标题翻译：具有嵌入式纠错码的存储器件的读取方法和具有嵌入式纠错码的存储器件
公开(公告)号：US08347201B2
公开(公告)日：2013-01-01
申请号：US13047678
申请日：2011-03-14
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F7/02 , H03M13/00
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并产生至少一个第二恢复字符串（S2-SN）。基于第一恢复串（S1）和第二恢复串（S2-SN）之间的比较，生成修改串（SM），其中存在擦除（X），并且至少一个第二解码尝试使用修改后的字符串（SM）进行。

36. 发明授权

US07937576B2 Configuration of a multi-level flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US07937576B2
公开(公告)日：2011-05-03
申请号：US11460777
申请日：2006-07-28
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以便执行存储器的不同功能算法。简化了测试过程中存储器件工作参数的最佳配置的识别通过在存储器件的每次上电时允许将配置位一次性处理成存储在嵌入式辅助随机存取存储器中的算法友好数据。这通过执行存储在存储器装置中的特定加电算法代码来完成嵌入式微处理器的辅助只读存储器。

37. 发明授权

US07908543B2 Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code 有权
标题翻译：具有嵌入式纠错码的存储器件的读取方法和具有嵌入式纠错码的存储器件
公开(公告)号：US07908543B2
公开(公告)日：2011-03-15
申请号：US11713376
申请日：2007-03-01
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS−1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并产生至少一个第二恢复字符串（S2-SN）。基于第一恢复串（S1）和第二恢复串（S2-SN）之间的比较，生成修改串（SM），其中存在擦除（X），并且至少一个第二解码尝试使用修改后的字符串（SM）进行。

38. 发明申请

US20080065937A1 NAND FLASH MEMORY DEVICE WITH ECC PROTECTED RESERVED AREA FOR NON-VOLATILE STORAGE OF REDUNDANCY DATA 审中-公开
标题翻译：具有ECC保护区域的NAND闪存存储器件，用于非易失存储冗余数据
公开(公告)号：US20080065937A1
公开(公告)日：2008-03-13
申请号：US11854685
申请日：2007-09-13
申请人： Rino Micheloni , Roberto Ravasio , Alessia Marelli
发明人： Rino Micheloni , Roberto Ravasio , Alessia Marelli
IPC分类号： G11C29/04
CPC分类号： G11C29/82 , G06F11/1068 , G11C29/24 , G11C2029/0411
摘要： Basic redundancy information is non-volatily stored in a reserved area of an addressable area of a memory array, and is copied to volatile storage therein at every power-on of the memory device. The unpredictable though statistically inevitable presence of failed array elements in such a reserved area of the memory array corrupts the basic redundancy information established during the test-on wafer (EWS) phase of the fabrication process. This increases the number of rejects, and lowers the yield of the fabrication process. This problem is addressed by writing the basic redundancy data in the reserved area of the array with an ECC technique using a certain error correction code. The error correction code may be chosen among majority codes 3, 5, 7, 15 and the like, or the Hamming code for 1, 2, 3 or more errors, as a function of the fail probability of a memory cell as determined by the EWS phase during fabrication.
摘要翻译：基本冗余信息被非挥发地存储在存储器阵列的可寻址区域的保留区域中，并且在存储器件的每次上电时复制到其中的易失性存储器。在存储器阵列的这种保留区域中，不可预测的，不可避免的存在故障阵列元件会破坏在制造过程的测试晶片（EWS）阶段期间建立的基本冗余信息。这增加了废品的数量，降低了制造工艺的产量。通过使用特定的纠错码通过ECC技术将阵列的保留区域中的基本冗余数据写入该问题来解决该问题。可以在多数代码3,5,7,15等之中选择纠错码，或者对于1,2,3或更多个错误，可以选择Hamming代码作为存储器单元的故障概率的函数，如由 EWS相制造期间。

39. 发明申请

US20080052458A1 NON-VOLATILE, ELECTRICALLY-PROGRAMMABLE MEMORY 有权
标题翻译：非易失性，电可编程存储器
公开(公告)号：US20080052458A1
公开(公告)日：2008-02-28
申请号：US11844465
申请日：2007-08-24
申请人： Rino Micheloni , Roberto Ravasio
发明人： Rino Micheloni , Roberto Ravasio
IPC分类号： G06F12/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C2211/5641
摘要： A solid-state mass storage device is provided. The solid-state mass storage device defines a storage area adapted to store data; the storage area is adapted to be exploited for storing data with a first storage density at a first data transfer speed. The storage area includes at least a first storage area portion and a second storage area portion. The solid-state mass storage device further includes accessing logic adapted to exploit the first storage area portion for storing data with a second storage density at a second data transfer speed, and adapted to exploit the second storage area portion for storing data with a third storage density and a third data transfer speed. The second storage density is lower than the third storage density, which is in turn lower than or equal to the first storage density; the second data transfer speed is higher than the third data transfer speed, which is in turn higher than or equal to the first data transfer speed.
摘要翻译：提供固态大容量存储装置。固态大容量存储装置定义适于存储数据的存储区域; 存储区域适于被利用以以第一数据传送速度存储具有第一存储密度的数据。存储区域至少包括第一存储区域部分和第二存储区域部分。固体大容量存储装置还包括访问逻辑，其适于利用第一存储区域部分以第二数据传输速度存储具有第二存储密度的数据，并且适于利用第二存储区域部分来存储具有第三存储器的数据密度和第三数据传输速度。第二储存密度低于第三储存密度，其又低于或等于第一储存密度; 第二数据传送速度高于第三数据传送速度，其又高于或等于第一数据传送速度。

40. 发明申请

US20080049521A1 METHOD FOR COMPACTING THE ERASED THRESHOLD VOLTAGE DISTRIBUTION OF FLASH MEMORY DEVICES DURING WRITING OPERATIONS 有权
标题翻译：写入操作期间闪存存储器件的擦除阈值电压分配方法
公开(公告)号：US20080049521A1
公开(公告)日：2008-02-28
申请号：US11844480
申请日：2007-08-24
申请人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
发明人： Rino Micheloni , Luca Crippa , Roberto Ravasio , Federico Pio
IPC分类号： G11C16/04
CPC分类号： G11C16/344
摘要： A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.
摘要翻译：一种用于操作闪存设备的方法。存储器件包括存储器单元矩阵，每个存储器单元具有限定存储在存储器单元中的值的可编程阈值电压。该方法包括以下步骤：擦除存储器单元块，以及在预定的压缩范围内压缩块的存储单元的阈值电压，其中压缩步骤包括：选择块写入的至少一个第一存储单元目标值将块的存储器单元的子集的阈值电压恢复到压缩范围，该子集包括与至少一个第一存储器相邻的块的至少一个第一存储器单元和/或至少一个第二存储器单元细胞; 并且至少部分地将目标值写入至少一个第一存储单元。

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