专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07085913B2 Hub/router for communication between cores using cartesian coordinates 失效
公开(公告)号：US07085913B2
公开(公告)日：2006-08-01
申请号：US09683778
申请日：2002-02-13
申请人： W. Riyon Harding , Sebastian T. Ventrone
发明人： W. Riyon Harding , Sebastian T. Ventrone
IPC分类号： G06F15/17 , G06F17/50
CPC分类号： G06F15/7832
摘要： A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs transfer data between the logic cores.

32. 发明授权

US07065602B2 Circuit and method for pipelined insertion 失效
标题翻译：流水线插入的电路和方法
公开(公告)号：US07065602B2
公开(公告)日：2006-06-20
申请号：US10604205
申请日：2003-07-01
申请人： Robert S. Horton , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Sebastian T. Ventrone
发明人： Robert S. Horton , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/14
CPC分类号： G06F13/4247 , H04L25/14
摘要： The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line
摘要翻译：本发明通过首先沿着分段数据线的第一段传播第一数据部分，然后沿着分段数据线的第二段传播第一数据部分并同时沿第二数据部分传播第二数据部分分段数据线的第一段。本发明将单个数据传输中断到这样的不同数据部分，并且随后将所有不同数据部分已经沿着分段数据线的所有部分单独发送，将不同的数据部分重新组合成单个数据传输

33. 发明授权

US06985004B2 Wiring optimizations for power 失效
公开(公告)号：US06985004B2
公开(公告)日：2006-01-10
申请号：US09781369
申请日：2001-02-12
申请人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John M. Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas M. Lepsic , Jagannathan Narasimhan , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： H03K17/16
CPC分类号： G06F17/5072 , G06F17/5022 , G06F17/5077
摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

34. 发明授权

US06954085B2 System and method for dynamically executing a function in a programmable logic array 失效
标题翻译：用于在可编程逻辑阵列中动态执行功能的系统和方法
公开(公告)号：US06954085B2
公开(公告)日：2005-10-11
申请号：US10605603
申请日：2003-10-13
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： G06F15/78 , H03K19/177 , H03K19/173
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17756 , H03K19/1776
摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.
摘要翻译：一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。当程序员使用下一个功能块重新配置功能区域并且重新配置用于接收下一个功能块的输出的一个存储区域时，从当前功能块传递到下一个功能块的数据被保存在其他存储区域。

35. 发明授权

US06711719B2 Method and apparatus for reducing power consumption in VLSI circuit designs 失效
标题翻译：用于降低VLSI电路设计中的功耗的方法和装置
公开(公告)号：US06711719B2
公开(公告)日：2004-03-23
申请号：US09928573
申请日：2001-08-13
申请人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
发明人： John Maxwell Cohn , Alvar A. Dean , Amir H. Farrahi , David J. Hathaway , Thomas Michael Lepsic , Patrick Edward Perry , Scott A. Tetreault , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.
摘要翻译：在集成电路（IC）设计中，功率消耗的分量可以表示为功率=½FCV <2>，其中C是由源单元驱动的负载电容，F是源单元的开关频率，V 是总输出电压摆幅。然而，不是由源单元产生的每个信号值都不需要传播到芯片的每个时钟周期连接到源的所有宿单元。因此，将隔离单元插入到将源单元连接到至少一个宿单元的网络（有线）中，以便当由所述源单元输出的信号从所述源单元输出时，将所述至少一个宿单元和所述网的一部分与所述源单元分离源不需要传播。由于去耦合，与至少一个接收器和净部分相关联的负载电容对于这种信号不被源单元体验。因此，整体IC功耗降低。

36. 发明授权

US06658634B1 Logic power optimization algorithm 失效
标题翻译：逻辑功率优化算法
公开(公告)号：US06658634B1
公开(公告)日：2003-12-02
申请号：US09073999
申请日：1998-05-07
申请人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Clarence R. Ogilvie , Wilbur D. Pricer , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5022 , G06F2217/78
摘要： Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.
摘要翻译：公开了一种用于消除在逻辑网络中不必要的逻辑切换的系统和方法。该方法和系统可以直接并入逻辑综合软件中，或者可以手动实现。提供了用于识别关键网络，然后在关键网络处插入网络锁存器的机制，其中每个网络锁存器由也控制相关输出锁存器的使能信号控制。每个网络锁存器包括一个电路，该电路可以在命令上保持给定逻辑节点上的最后一个逻辑电平。

37. 发明授权

US06412096B1 Method and apparatus for a hedge analysis technique for performance improvements of large scale integrated circuit logic design 失效
标题翻译：用于大规模集成电路逻辑设计性能改进的对冲分析技术的方法和装置
公开(公告)号：US06412096B1
公开(公告)日：2002-06-25
申请号：US09303154
申请日：1999-04-30
申请人： Sebastian T. Ventrone
发明人： Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/505
摘要： An apparatus and method for performing a Hedge Technique Analysis are used to enhance the performance of the functional logic design of a large scale integrated circuit while simplifying the underlying logic. The methodology first runs performance tests on the logic circuitry to assess the timing and characterize the logic paths; next, functional paths are identified and listed; common logic path leaves, twigs, and branches are then identified and ranked by the number of critical paths associated with each; all high ranking common logic path leaves, twigs, and branches are then collapsed; and, timing paths are re-run to characterize the final performance rating of the functional design.
摘要翻译：用于执行对冲技术分析的装置和方法用于增强大规模集成电路的功能逻辑设计的性能，同时简化基础逻辑。该方法首先对逻辑电路执行性能测试，以评估逻辑路径的时序和特征; 接下来，确定并列出功能路径; 然后通过与每个相关联的关键路径的数量来识别和分级通用逻辑路径叶，树枝和分支; 然后，所有高排名的常见逻辑路径叶，树枝和树枝都崩溃了; 并且重新运行定时路径以表征功能设计的最终性能等级。

38. 发明授权

US06304122B1 Low power LSSD flip flops and a flushable single clock splitter for flip flops 失效
标题翻译：低功率LSSD触发器和可触发单触发器的单个时钟分配器
公开(公告)号：US06304122B1
公开(公告)日：2001-10-16
申请号：US09641425
申请日：2000-08-17
申请人： Roger P. Gregor , Steven F. Oakland , Toshiharu Saitoh , Sebastian T. Ventrone
发明人： Roger P. Gregor , Steven F. Oakland , Toshiharu Saitoh , Sebastian T. Ventrone
IPC分类号： H03K3289
CPC分类号： H03K3/0375 , H03K3/0372
摘要： This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.
摘要翻译：本发明通过提供具有比现有技术的触发器更少的时钟树的触发器装置来降低触发器装置的功率，但仍然支持一些或全部级别敏感扫描设计（LSSD）功能。在本发明的优选实施例中，使用一个时钟树来代替两个时钟树来提供较低的功率，并且使用时钟分配器中的较少的开关器件，其也提供较低的功率。另外，提供了一个可冲洗的单时钟分离器，其允许一个时钟树被使用到可冲洗的单时钟分离器，并且在可冲洗单时钟分离器的输出端上提供两个时钟。这节省了一些功耗，但仍然允许双时钟触发器设计。

39. 发明授权

US06253299B1 Virtual cache registers with selectable width for accommodating different precision data formats 失效
标题翻译：具有可选宽度的虚拟缓存寄存器，以适应不同精度的数据格式
公开(公告)号：US06253299B1
公开(公告)日：2001-06-26
申请号：US09224793
申请日：1999-01-04
申请人： Jack R. Smith , Sebastian T. Ventrone , Keith R. Williams
发明人： Jack R. Smith , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F1200
CPC分类号： G06F9/30112 , G06F9/30036 , G06F9/3013 , G06F9/30138 , G06F12/0875
摘要： A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.
摘要翻译：用于处理数据的结构和方法包括具有基本高速缓存，具有基本宽度并且可操作地连接到处理单元的基本寄存器的处理单元和具有虚拟宽度并位于基本高速缓存中并可操作地连接到所述处理单元，其中所述处理系统的基本处理精度由所述基本寄存器的基本宽度确定，并且可选择的增强处理精度由所述虚拟高速缓存寄存器的虚拟宽度确定，其中所述基本寄存器存储基本指令和数据并且所述虚拟高速缓存寄存器存储增强数据，所述虚拟宽度大于所述基本宽度，并且其中所述基本高速缓存包括标识所述基本高速缓存的一部分作为所述虚拟寄存器的标签，所述虚拟高速缓存寄存器仅由所述处理单元访问执行增强的指令以提供增强的处理精度。

40. 发明授权

US6097243A Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode 有权
标题翻译：使用低功耗模式降低集成半导体器件功耗的装置和方法
公开(公告)号：US6097243A
公开(公告)日：2000-08-01
申请号：US159861
申请日：1998-09-24
申请人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
发明人： Claude L. Bertin , William Robert Patrick Tonti , Alvar Antonio Dean , Wilbur David Pricer , Patrick Edward Perry , Kenneth J. Goodnow , Sebastian T. Ventrone
IPC分类号： G05F1/08 , G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.
摘要翻译：根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。优选实施例通过利用上拉或下拉晶体管将电路中的输入引导到在电路不活动的时段期间最小化功耗的状态来减少电路中的不需要的节点切换。通过在不活动状态下将电路输入高或低，在该电路中节点切换被减少或消除。在优选实施例中，电路的输入在与电路中最漏电晶体管的漏电流成比例的不活动时间之后全部被拉。通过定时输入拉动与泄漏电流成比例，最大限度地减少功耗，而不会由拉动本身引起的功率损耗过大。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式