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31. 发明授权

US06798688B2 Storage array such as a SRAM with reduced power requirements 有权
公开(公告)号：US06798688B2
公开(公告)日：2004-09-28
申请号：US10306938
申请日：2002-11-29
申请人： Rajiv V. Joshi
发明人： Rajiv V. Joshi
IPC分类号： G11C1100
CPC分类号： G11C11/413 , G11C8/08
摘要： A CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI) and may include fully depleted (FD) FETs. A power line supply select at each row selectively increases cell supply voltage to a full supply voltage when the row is selected. A word line decoder selects a row of cells that are provided the supply voltage and cells in remaining rows are provided a reduced supply voltage. Leakage is substantially lower in said remaining rows than in said selected row. The sense amplifier may include cross coupled FD NFETs sensing stored data. A read/write-select in each bit path selectively blocks cell writes when cell contents are not being changed. Power is not expended unnecessarily writing to cells.

32. 发明授权

US06789099B2 Sense-amp based adder with source follower evaluation tree 有权
公开(公告)号：US06789099B2
公开(公告)日：2004-09-07
申请号：US10167170
申请日：2002-06-10
申请人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
发明人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
IPC分类号： G06F750
CPC分类号： G06F7/508 , G06F7/503 , G06F7/507 , G06F2207/3872 , G06F2207/4814
摘要： A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

33. 发明授权

US06683805B2 Suppression of leakage currents in VLSI logic and memory circuits 有权
标题翻译： VLSI逻辑和存储器电路中泄漏电流的抑制
公开(公告)号：US06683805B2
公开(公告)日：2004-01-27
申请号：US10067411
申请日：2002-02-05
申请人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
发明人： Rajiv V. Joshi , Louis L. Hsu , Azeez J. Bhavnagarwala
IPC分类号： G11C11413
CPC分类号： G11C11/412
摘要： An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.
摘要翻译：提供一种SRAM系统，其具有包括至少一个接收第一电源电压的电池的SRAM单元阵列和用于向至少一个电路的至少一个选定电路提供第二电源电压的功率控制电路。该系统是存储器阵列和逻辑系统之一，并且至少一个电路的电路是存储器阵列的存储单元，存储器阵列的读出放大器和逻辑系统的路径之一。还提供了一种用于向系统的至少一个电路提供电源电压的方法。

34. 发明授权

US06617702B2 Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate 有权
标题翻译：半导体器件利用对准标记来全面对准半导体衬底的正面和背面
公开(公告)号：US06617702B2
公开(公告)日：2003-09-09
申请号：US09769080
申请日：2001-01-25
申请人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
发明人： Louis L. Hsu , Rajiv V. Joshi , Carl Radens , Jack A. Mandelman , Tsorng-Dih Yuan
IPC分类号： H01L23544
CPC分类号： H01L23/48 , H01L21/8221 , H01L23/544 , H01L24/48 , H01L24/73 , H01L27/0694 , H01L2223/54473 , H01L2224/05599 , H01L2224/16225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , Y10T29/49133 , Y10T29/49155 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
摘要翻译：本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。

35. 发明授权

US5617047A Reset and pulse width control circuits for high-performance multi-port memories and register files 失效
标题翻译：用于高性能多端口存储器和寄存器文件的复位和脉冲宽度控制电路
公开(公告)号：US5617047A
公开(公告)日：1997-04-01
申请号：US468173
申请日：1995-06-06
申请人： Walter H. Henkels , Wei Hwang , Rajiv V. Joshi
发明人： Walter H. Henkels , Wei Hwang , Rajiv V. Joshi
IPC分类号： G11C7/22 , G11C8/18 , H03K3/356 , H03K3/01
CPC分类号： G11C8/18 , G11C7/22 , H03K3/356026 , H03K3/356113
摘要： A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.
摘要翻译：单个顺序定时链提供了复位脉冲定时精度不足和针对高性能存储器或包含动态电路的寄存器文件的复位脉冲宽度控制不足。此外，在这样的电路中，从输入到输出的脉冲不可避免地延长。所公开的多分支电路消除了这些缺点，这些电路提供适当的控制脉冲的产生，并且通过使用与控制发电电路适当互连的评估路径脉宽缩短电路。

36. 发明授权

US5426330A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5426330A
公开(公告)日：1995-06-20
申请号：US125107
申请日：1993-09-21
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.
摘要翻译：一种器件包括衬底，位于所述衬底上的至少一个电介质层和位于所述至少一个介电层中的开口中的金属化，并且从与所述衬底的表面基本上共面的表面向所述衬底延伸预定距离至少一个介电层。金属化包括由难熔金属或合金包覆的低电阻率金属或合金，其电阻率大于低电阻率金属或合金的电阻率，并具有柱状结构。金属化具有多个横截面，多个侧面的至少三个边基本上由具有共同成分的难熔金属或合金形成，多个侧面的至少两侧基本上延伸预定距离，并且所述多个侧面中的所有多个侧面形成在所述至少一个介电层中的开口内。

37. 发明授权

US5300813A Refractory metal capped low resistivity metal conductor lines and vias 失效
$Refractory metal capped low resistivity metal conductor lines and vias$
标题翻译：耐火金属封盖的低电阻金属导线和通孔
公开(公告)号：US5300813A
公开(公告)日：1994-04-05
申请号：US841967
申请日：1992-02-26
申请人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
发明人： Rajiv V. Joshi , Jerome J. Cuomo , Hormazdyar M. Dalal , Louis L. Hsu
IPC分类号： H01L21/28 , H01L21/312 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532 , H01L29/440 , H01L29/460
CPC分类号： H01L21/76843 , H01L21/76838 , H01L21/7684 , H01L21/76847 , H01L21/76849 , H01L21/76852 , H01L21/76877 , H01L23/49866 , H01L23/53223 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/09701 , Y10S148/015 , Y10S257/915 , Y10S438/959
摘要： A contact structure for a semiconductor device having a first refractory metal layer formed only at the bottom of a contact hole. The first refractory metal is selected from a group comprising titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys or some other suitable material. A low resistivity layer comprising a single, binary or ternary metalization is deposited over the first refractory metal layer in the contact hole by a method such as PVD using evaporation or collimated sputtering. The low resistivity layer has side walls which taper inwardly toward one another with increasing height of the layer and the low resistivity layer does not contact the side walls of the contact hole. The low resistivity layer may be Al.sub.x Cu.sub.y (x+y=1; x.gtoreq.0, y.gtoreq.0), ternary alloys such as Al-Pd-Cu or multicomponent alloys such as Al-Pd-Nb-Au. A second refractory metal layer is deposited over the low resistivity layer. The second refractory metal layer may be tungsten, cobalt, nickel, molybdenum or alloys/compounds such as Ti/TiN. The first and second refractory metal layers completely encapsulate the low resistivity layer. The first and second refractory metal layers can comprise an alloy containing silicon with a higher incorporated silicon content near the top of the contact hold present as a distinct or graded composition than at a location closer to the bottom of the contact hole.
摘要翻译：一种用于半导体器件的接触结构，其具有仅在接触孔的底部形成的第一难熔金属层。第一难熔金属选自钛（Ti），钛合金或Ti / TiN，钨（W），钛/钨（Ti / W）合金或铬（Cr）或钽（Ta）及其合金或其他合适的材料。包含单一二元或三元金属化的低电阻率层通过诸如使用蒸发或准直溅射的PVD的方法沉积在接触孔中的第一难熔金属层上。低电阻率层具有随着层的高度逐渐向内逐渐向内逐渐变细的侧壁，低电阻层不接触接触孔的侧壁。低电阻率层可以是AlxCuy（x + y = 1; x> = 0，y> = 0），诸如Al-Pd-Cu的三元合金或诸如Al-Pd-Nb-Au的多组分合金。在低电阻率层上沉积第二难熔金属层。第二耐火金属层可以是钨，钴，镍，钼或诸如Ti / TiN的合金/化合物。第一和第二难熔金属层完全封装低电阻率层。第一和第二难熔金属层可以包含含有硅的合金，其中接合保持层的顶部附近具有更高的掺入硅含量，作为不同或分级的组成，而不是靠近接触孔底部的位置。

38. 发明授权

US4617087A Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits 失效
标题翻译：用于在集成半导体电路中用于制造金属触点的金属的差分选择性沉积的方法
公开(公告)号：US4617087A
公开(公告)日：1986-10-14
申请号：US780871
申请日：1985-09-27
申请人： Subramanian S. Iyer , Rajiv V. Joshi
发明人： Subramanian S. Iyer , Rajiv V. Joshi
IPC分类号： H01L21/3205 , C23C16/02 , C23C16/04 , C23C16/06 , C23F4/00 , H01L21/28 , H01L21/285 , H01L21/768 , C23F1/02 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76879 , C23C16/0281 , C23C16/04 , C23C16/06 , C23F4/00 , H01L21/28562
摘要： A deposition technique for forming metal regions on semiconductor substrates, and more particularly to a fabrication method for the differential selective deposition of tungsten for forming tungsten contacts on an integrated circuit chip.Tungsten hexafluoride gas (WF6) is introduced into a deposition chamber containing a silicon substrate with an apertured silicon dioxide mask layer thereon. The exposed Si surfaces on which the selective deposition is to be performed, are first converted to W surfaces by the substitution reaction:2WF6+3Si=2W+3SiF4After the surface has been substituted, the WF.sub.6 is mixed with H.sub.2 as to give deposition of W by partially preferential nucleation on the already converted W surfaces. Then NF.sub.3 is bled into the system and a plasma is struck in the reaction chamber to create a simultaneous etching condition for the tungsten.The amount of NF3 and the plasma power coupled into the chamber are such as to ensure that the SiO.sub.2 surface is kept clean at all times. Thus any nuclei that may be formed on the SiO.sub.2 surface, are immediately cleaned out. Since the deposition rate on the exposed W surfaces is much higher than on the SiO.sub.2 surfaces, there will be net deposition on these areas in spite of the etching action, albeit at a lower rate.
摘要翻译：一种用于在半导体衬底上形成金属区域的沉积技术，更具体地说，涉及用于在集成电路芯片上形成钨触点的钨的差分选择性沉积的制造方法。将六氟化钨气体（WF6）引入到其中具有带孔二氧化硅掩模层的硅衬底的沉积室中。要进行选择性沉积的暴露的Si表面首先通过取代反应转化为W表面：2WF6 + 3Si = 2W + 3SiF4在表面被取代后，将WF6与H 2混合，使沉积 W在已经转化的W表面上部分优先成核。然后将NF3放入系统中，并在反应室中撞击等离子体，以产生钨的同时蚀刻条件。 NF3的量和耦合到腔室中的等离子体功率是确保SiO 2表面始终保持清洁。因此，可以立即清除可能形成在SiO2表面上的任何核。由于暴露的W表面上的沉积速率远高于SiO 2表面上的沉积速率，尽管蚀刻作用仍然存在这些区域上的净沉积，尽管速率较低。

39. 发明授权

US09454629B2 Fet-bounding for fast TCAD-based variation modeling 有权
标题翻译：快速基于TCAD的变异建模
公开(公告)号：US09454629B2
公开(公告)日：2016-09-27
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

40. 发明授权

US08941110B2 E-fuses containing at least one underlying tungsten contact for programming 有权
标题翻译：电子熔丝包含至少一个底层钨触点用于编程
公开(公告)号：US08941110B2
公开(公告)日：2015-01-27
申请号：US13298872
申请日：2011-11-17
申请人： Rajiv V. Joshi , Chih-Chao Yang
发明人： Rajiv V. Joshi , Chih-Chao Yang
IPC分类号： H01L23/525 , H01L23/528 , H01L23/532 , H01L45/00 , H01L27/24 , H01L23/522
CPC分类号： H01L21/768 , H01L23/5226 , H01L23/5256 , H01L23/53257 , H01L27/11206 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/16 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.
摘要翻译：提供了包括电子熔丝（E熔丝）的半导体结构，其包括用于编程熔丝元件的熔丝元件和至少一个下层钨触点。在一些实施例中，使用一对相邻的钨触点来编程熔丝元件。在另一个实施例中，覆盖的导电区域可与下面的钨触点中的一个结合使用以对熔丝元件进行编程。在所公开的结构中，熔丝元件与一对底层钨触点的上表面直接接触。在一个实施例中，半导体结构可以包括位于熔丝元件顶部的互连级。互连电平具有嵌入其中的多个导电区域。在其他实施例中，熔丝元件位于位于钨触点顶部的互连级内。

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