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31. 发明申请

US20110180212A1 Plasma Processing Chamber for Bevel Edge Processing 有权
标题翻译：斜边处理等离子处理室
公开(公告)号：US20110180212A1
公开(公告)日：2011-07-28
申请号：US13082393
申请日：2011-04-07
申请人： Andrew D. Bailey, III , Yunsang Kim
发明人： Andrew D. Bailey, III , Yunsang Kim
IPC分类号： H01L21/3065
CPC分类号： H01J37/32385 , H01J37/321 , H01J37/32366 , H01J37/32706 , H01L21/02087 , H01L21/67069 , H01L21/6715
摘要： Chambers for processing a bevel edge of a substrate are provided. One such chamber includes a bottom electrode defined to support a substrate in the chamber. The bottom electrode has a bottom first level for supporting the substrate and a bottom second level near an outer edge of bottom electrode. The bottom second level is defined at a step below the bottom first level. Further included is a top electrode oriented above the bottom electrode. The top electrode having a top first level and a top second level, where the top first level is opposite the bottom first level and the top second level is opposite the bottom second level. The top second level is defined at a step above the top first level. A bottom ring mount oriented at the bottom second level is included. The bottom ring mount includes a first adjuster for moving a bottom permanent magnet toward and away from the top electrode. Further included is a top ring mount oriented at the top second level. The top ring mount includes a second adjuster for moving a top permanent magnet toward and away from the bottom electrode.
摘要翻译：提供了用于处理基板的斜边缘的室。一个这样的室包括限定为支撑室中的衬底的底部电极。底部电极具有用于支撑衬底的底部第一电平和底部电极的外部边缘附近的底部第二电平。底部第二级别定义在底层第一级以下的一级。还包括位于底部电极上方的顶部电极。顶部电极具有顶部第一电平和顶部第二电平，其中顶部第一电平与底部第一电平相反，而顶部第二电平与底部第二电平相反。顶级的第二级是在顶级第一级以上的一级定义的。包括位于底部第二级的底环安装座。底环安装件包括用于使底部永磁体朝向和远离顶部电极移动的第一调节器。另外还包括一个位于顶部第二层的顶环安装座。顶环安装件包括用于使顶部永磁体朝向和远离底部电极移动的第二调节器。

32. 发明授权

US07959984B2 Methods and arrangement for the reduction of byproduct deposition in a plasma processing system 有权
标题翻译：在等离子体处理系统中减少副产物沉积的方法和装置
公开(公告)号：US07959984B2
公开(公告)日：2011-06-14
申请号：US11022982
申请日：2004-12-22
申请人： Shrikant P. Lohokare , Andrew D. Bailey, III
发明人： Shrikant P. Lohokare , Andrew D. Bailey, III
IPC分类号： H05H1/24
CPC分类号： H01J37/32633 , C23C16/4404 , H01J37/32623
摘要： In a plasma processing system, a method of reducing byproduct deposits on a set of plasma chamber surfaces of a plasma processing chamber is disclosed. The method includes providing a deposition barrier in the plasma processing chamber, the deposition barrier is configured to be disposed in a plasma generating region of the plasma processing chamber, thereby permitting at least some process byproducts produced when a plasma is struck within the plasma processing chamber to adhere to the deposition barrier and reducing the byproduct deposits on the set of plasma processing chamber surfaces.
摘要翻译：在等离子体处理系统中，公开了一种在等离子体处理室的一组等离子体室表面上减少副产物沉积的方法。所述方法包括在所述等离子体处理室中设置沉积阻挡层，所述沉积阻挡层被配置为设置在所述等离子体处理室的等离子体产生区域中，从而允许在所述等离子体处理室内等离子体被击中时产生的至少一些过程副产物以附着到沉积屏障上并减少等离子体处理室表面组上的副产物沉积物。

33. 发明申请

US20100096087A1 Apparatus For Aligning Electrodes In A Process Chamber to Protect An Exclusion Area Within An Edge Environ Of A Wafer 有权
标题翻译：用于使电极对准处理室中用于保护晶片边缘环境内的排除区域的装置
公开(公告)号：US20100096087A1
公开(公告)日：2010-04-22
申请号：US12647301
申请日：2009-12-24
申请人： Gregory S. Sexton , Andrew D. Bailey, III , Alan M. Schoepp , John D. Boniface
发明人： Gregory S. Sexton , Andrew D. Bailey, III , Alan M. Schoepp , John D. Boniface
IPC分类号： H01L21/306
CPC分类号： H01L21/67069 , H01J37/32568
摘要： Positional relationships are established in a process chamber. A base is configured with a lower electrode surface to support a wafer, and an upper electrode has a lower surface. A drive mounted on the base has a linkage connected to the upper electrode. A fixture placed on the lower surface moves into a desired orientation of the lower electrode. With the upper electrode loosely connected by the linkage to the drive, the fixture transfers the desired orientation to the upper electrode. The linkage is tightened to maintain the desired orientation, the fixture is removed and a process exclusion insert is mounted to the upper electrode. The drive moves the upper electrode and the insert to define an inactive process zone between the upper electrode and the wafer on the lower electrode to protect a central area of the wafer during etching of a wafer edge environ around the central area.
摘要翻译：位置关系建立在一个过程室中。基底配置有下电极表面以支撑晶片，并且上电极具有下表面。安装在基座上的驱动器具有连接到上电极的连杆。放置在下表面上的固定器移动到下电极的期望取向。通过与驱动器的联动松动地连接上电极，固定装置将期望的方向传送到上电极。连接件被拧紧以保持所需的取向，夹具被移除，并且将过程排除插入件安装到上电极。驱动器移动上电极和插入件以在下电极上的上电极和晶片之间限定非活动的工艺区域，以在蚀刻围绕中心区域的晶片边缘环境时保护晶片的中心区域。

34. 发明授权

US07653515B2 Expert knowledge methods and systems for data analysis 有权
标题翻译：专家知识方法和数据分析系统
公开(公告)号：US07653515B2
公开(公告)日：2010-01-26
申请号：US11698400
申请日：2007-01-25
申请人： Puneet Yadav , Andrew D. Bailey, III
发明人： Puneet Yadav , Andrew D. Bailey, III
IPC分类号： G06F19/00
CPC分类号： G05B19/41875 , G05B2219/31352 , G05B2219/32191 , Y02P90/22
摘要： A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received. A new data set corresponding to one process run is received. The new data set is projected to the model. An outlier data point produced as a result of the projecting is identified. A variable corresponding to the one outlier data point is identified, the identified variable exhibiting a high contribution. A value for the variable from the new data set is identified. Whether the value for the variable is unimportant is determined. A normalized matrix of data is created, using random data and the variable that was determined to be unimportant from each of the new data set and the data set. The data set is updated with the normalized matrix of data.
摘要翻译：提供一种用于调整定义一组处理运行的数据集的方法，每个处理运行具有与用于晶片处理操作的一组变量相对应的一组数据。接收从数据集导出的模型。接收对应于一个进程运行的新数据集。新数据集投影到模型中。识别作为投影结果产生的异常值数据点。识别与一个异常数据点对应的变量，所识别的变量表现出高贡献。识别来自新数据集的变量的值。确定变量的值是否不重要。使用随机数据和被确定为与每个新数据集和数据集不重要的变量来创建数据的归一化矩阵。数据集用数据的归一化矩阵更新。

35. 发明申请

US20090170334A1 Copper Discoloration Prevention Following Bevel Etch Process 审中-公开
标题翻译：铜蚀变过程中的铜变色防止
公开(公告)号：US20090170334A1
公开(公告)日：2009-07-02
申请号：US12341384
申请日：2008-12-22
申请人： Tong Fang , Andrew D. Bailey, III , Yunsang Kim , Olivier Rigoutat , George Stojakovic
发明人： Tong Fang , Andrew D. Bailey, III , Yunsang Kim , Olivier Rigoutat , George Stojakovic
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01J37/32366 , H01L21/02068 , H01L21/02087 , H01L21/32136 , H01L21/6708
摘要： A method of bevel edge etching a semiconductor substrate having exposed copper surfaces with a fluorine-containing plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the fluorine-containing plasma in the bevel etcher; evacuating the bevel etcher after the bevel edge etching is completed; flowing defluorinating gas into the bevel etcher; energizing the defluorinating gas into a defluorination plasma at a periphery of the semiconductor substrate; and processing the semiconductor substrate with the defluorination plasma under conditions to prevent discoloration of the exposed copper surfaces of the semiconductor substrate upon exposure, the discoloration occurring upon prolonged exposure to air.
摘要翻译：在半导体衬底支撑在半导体衬底支撑体上的斜面蚀刻器中，使用具有含氟等离子体的具有暴露的铜表面的半导体衬底进行斜边蚀刻的方法包括：在半导体衬底支撑体中的含氟等离子体斜角蚀刻机在斜边蚀刻完成之后排空斜面蚀刻机; 将脱氟气体流入斜面蚀刻机; 在所述半导体衬底的外围将所述脱氟气体通电为脱氟等离子体; 并且在曝光时防止半导体衬底的暴露的铜表面的变色的条件下，用脱氟等离子体处理半导体衬底，在长时间暴露于空气时发生变色。

36. 发明授权

US07540935B2 Plasma oxidation and removal of oxidized material 失效
标题翻译：氧化物质的等离子体氧化和去除
公开(公告)号：US07540935B2
公开(公告)日：2009-06-02
申请号：US11076725
申请日：2005-03-09
申请人： Yunsang Kim , Andrew D. Bailey, III , Hyungsuk Alexander Yoon , Arthur M. Howald
发明人： Yunsang Kim , Andrew D. Bailey, III , Hyungsuk Alexander Yoon , Arthur M. Howald
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/31683 , H01L21/321 , H01L21/32115 , H01L21/32135 , H01L21/32138 , H01L21/32139 , H01L21/7684 , H01L21/76865 , H01L21/76885
摘要： A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. A system for etching a conductive layer is also disclosed.
摘要翻译：蚀刻导电层的方法包括转换导电层的至少一部分并蚀刻导电层，以基本上去除导电层的转换部分，从而暴露出剩余的表面。剩余的表面具有小于约10nm的平均表面粗糙度。还公开了用于蚀刻导电层的系统。

37. 发明授权

US07282909B2 Methods and apparatus for determining the thickness of a conductive layer on a substrate 有权
标题翻译：用于确定衬底上的导电层的厚度的方法和装置
公开(公告)号：US07282909B2
公开(公告)日：2007-10-16
申请号：US11172017
申请日：2005-06-29
申请人： Andrew D. Bailey, III
发明人： Andrew D. Bailey, III
IPC分类号： G01B7/06 , G01R33/12
CPC分类号： G01B7/105 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method of determining the thickness of a conductive film is disclosed. The method employs measured voltage and current responses that have been temperature-compensated to determine the thickness of the conductive film. The temperature compensation uses a temperature compensation factor obtained from a calibration substrate different from the target substrate on which the conductive film being measured is disposed. The calibration substrate has a conductive film formed of a conductive material that is substantially similar to the conductive material of the target substrate.
摘要翻译：公开了确定导电膜厚度的方法。该方法采用经过温度补偿的测量电压和电流响应来确定导电膜的厚度。温度补偿使用从与其上设置有测量导电膜的目标衬底不同的校准衬底获得的温度补偿因子。校准基板具有由导电材料形成的导电膜，其基本上类似于目标基板的导电材料。

38. 发明授权

US06939796B2 System, method and apparatus for improved global dual-damascene planarization 有权
标题翻译：用于改进全局双镶嵌平面化的系统，方法和装置
公开(公告)号：US06939796B2
公开(公告)日：2005-09-06
申请号：US10390117
申请日：2003-03-14
申请人： Shrikant P. Lohokare , Andrew D. Bailey, III , David Hemker , Joel M. Cook
发明人： Shrikant P. Lohokare , Andrew D. Bailey, III , David Hemker , Joel M. Cook
IPC分类号： B44C1/22 , H01L20060101 , H01L21/302 , H01L21/304 , H01L21/311 , H01L21/321 , H01L21/3213 , H01L21/4763 , H01L21/768 , H01L33/00
CPC分类号： H01L21/7684 , H01L21/31116 , H01L21/32115 , H01L21/32135 , H01L21/32136
摘要： A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.
摘要翻译：用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。图案化半导体衬底具有填充图案中的多个特征的导电互连材料。导电互连材料具有覆盖层部分。覆盖层部分具有局部不均匀性。去除覆盖层部分的大部分以平坦化上覆层部分。映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

39. 发明授权

US06341574B1 Plasma processing systems 有权
标题翻译：等离子体处理系统
公开(公告)号：US06341574B1
公开(公告)日：2002-01-29
申请号：US09439661
申请日：1999-11-15
申请人： Andrew D. Bailey, III , Alan M. Schoepp , David J. Hemker , Mark H. Wilcoxson , Andras Kuthi
发明人： Andrew D. Bailey, III , Alan M. Schoepp , David J. Hemker , Mark H. Wilcoxson , Andras Kuthi
IPC分类号： C23C1600
CPC分类号： H01J37/32623 , H01J37/3266
摘要： A plasma processing system for processing a substrate which includes a single chamber, substantially azimuthally symmetric plasma processing chamber within which a plasma is both ignited and sustained for the processing. The plasma processing chamber has no separate plasma generation chamber. The plasma processing chamber has an upper end and a lower end. The plasma processing system includes a coupling window disposed at an upper end of the plasma processing chamber and an RF antenna arrangement disposed above a plane defined by the substrate when the substrate is disposed within the plasma processing chamber for the processing. The plasma processing system also includes an electromagnet arrangement disposed above the plane defined by the substrate. The electromagnet arrangement is configured so as to result in a radial variation in the controllable magnetic field within the plasma processing chamber in the region proximate the coupling window and antenna when at least one direct current is supplied to the electromagnet arrangement. The radial variation is effective to affect processing uniformity across the substrate. The plasma processing system additionally includes a dc power supply coupled to the electromagnet arrangement. The dc power supply has a controller to vary a magnitude of at least one direct current, thereby changing the radial variation in the controllable magnetic field within the plasma processing chamber in the region proximate the antenna to improve the processing uniformity across the substrate.
摘要翻译：一种用于处理衬底的等离子体处理系统，其包括单室，基本方位对称的等离子体处理室，其中等离子体都被点燃并持续进行处理。等离子体处理室没有单独的等离子体产生室。等离子体处理室具有上端和下端。等离子体处理系统包括设置在等离子体处理室的上端的耦合窗口和当衬底设置在等离子体处理室内用于处理时设置在由衬底限定的平面上方的RF天线布置。等离子体处理系统还包括设置在由衬底限定的平面之上的电磁体装置。当至少一个直流电被提供给电磁体装置时，电磁体装置构造成导致等离子体处理室内的可耦合窗口和天线附近的区域内的可控磁场的径向变化。径向变化对影响衬底上的加工均匀性是有效的。等离子体处理系统还包括耦合到电磁体装置的直流电源。直流电源具有控制器来改变至少一个直流电流的大小，从而改变等离子体处理室内靠近天线的可控磁场中的径向变化，以改善穿过衬底的加工均匀性。

40. 发明授权

US06320320B1 Method and apparatus for producing uniform process rates 有权
标题翻译：用于产生均匀加工速率的方法和装置
公开(公告)号：US06320320B1
公开(公告)日：2001-11-20
申请号：US09440418
申请日：1999-11-15
申请人： Andrew D. Bailey, III , Alan M. Schoepp , Andras Kuthi
发明人： Andrew D. Bailey, III , Alan M. Schoepp , Andras Kuthi
IPC分类号： H01J724
CPC分类号： H01J37/32467 , H01J37/321
摘要： A plasma processing apparatus for processing a substrate with a plasma is disclosed. The apparatus includes a first RF power source having a first RF frequency, and a process chamber. Further, the apparatus includes a substantially circular antenna operatively coupled to the first RF power source and disposed above a plane defined by the substrate when the substrate is disposed within the process chamber for processing. The substantially circular antenna being configured to induce an electric field inside the process chamber with a first RF energy generated by the first RF power source. The substantially circular antenna including at least a first pair of concentric loops in a first plane and a second pair of concentric loops in a second plane. The first pair of concentric loops and the second pair of concentric loops being substantially identical and symmetrically aligned with one another. The substantially circular antenna forming an azimuthally symmetric plasma inside the process chamber. The apparatus also includes a coupling window disposed between the antenna and the process chamber. The coupling window being configured to allow the passage of the first RF energy from the antenna to the interior of the process chamber. The coupling window having a first layer and a second layer. The second layer being configured to substantially suppress the capacitive coupling formed between the substantially circular antenna and the plasma. The substantially circular antenna and the coupling window working together to produce a substantially uniform process rate across the surface of the substrate.
摘要翻译：公开了一种用等离子体处理衬底的等离子体处理装置。该装置包括具有第一RF频率的第一RF电源和处理室。此外，该设备包括可操作地耦合到第一RF电源并且当基板设置在处理室内以进行处理时设置在由基板限定的平面之上的基本圆形的天线。基本上圆形的天线被配置为利用由第一RF电源产生的第一RF能量来诱导处理室内的电场。基本上圆形的天线包括第一平面中的至少第一对同心环和在第二平面中的第二对同心环。第一对同心环和第二对同心环彼此基本相同和对称地对准。大致圆形天线在处理室内形成方位对称等离子体。该装置还包括设置在天线和处理室之间的耦合窗口。耦合窗口被配置为允许第一RF能量从天线通过到处理室的内部。耦合窗具有第一层和第二层。第二层被配置为基本上抑制形成在基本上圆形的天线和等离子体之间的电容耦合。基本上圆形的天线和耦合窗口一起工作，以在衬底的表面上产生基本均匀的工艺速率。

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