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31. 发明授权

US06984580B2 Dual damascene pattern liner 有权
标题翻译：双镶嵌图案衬垫
公开(公告)号：US06984580B2
公开(公告)日：2006-01-10
申请号：US10789338
申请日：2004-02-26
申请人： William W. Dostalik , Robert Kraft , Kenneth D. Brennan
发明人： William W. Dostalik , Robert Kraft , Kenneth D. Brennan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76831 , H01L21/76844 , H01L21/76865 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An embodiment of the invention is a dual damascene layer 13 of an integrated circuit 2 containing a dual damascene pattern liner 21. Another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layer 13 where a dual damascene pattern liner 21 is formed over a cap layer 25 and within trench spaces.
摘要翻译：本发明的实施例是集成电路2的双镶嵌层13，其包含双镶嵌图案衬垫21。本发明的另一个实施方案是一种制造双镶嵌层13的方法，其中双层镶嵌图案衬垫21形成在覆盖层25之上和通孔内。本发明的另一个实施例是一种制造双镶嵌层13的方法，其中双层镶嵌图案衬垫21形成在覆盖层25之上和沟槽空间内。

32. 发明授权

US06362111B1 Tunable gate linewidth reduction process 有权
标题翻译：可调节门极线减少过程
公开(公告)号：US06362111B1
公开(公告)日：2002-03-26
申请号：US09382519
申请日：1999-08-25
申请人： Reima Laaksonen , Robert Kraft , James B. Friedmann
发明人： Reima Laaksonen , Robert Kraft , James B. Friedmann
IPC分类号： H01L21302
CPC分类号： H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A process for forming a polysilicon line having linewidths below 0.23 &mgr;m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., deep UV lithography). The BARC layer (30) is etched with an etch chemistry of HBr/O2 using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using the same etch chemistry having a selectivity of approximately one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below the practical resolution limit of the lithography tool. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).
摘要翻译：一种形成线宽低于0.23μm的多晶硅线的工艺。多晶硅层（20）沉积在半导体本体（10）上。一层底部抗反射涂层（BARC）（30）沉积在多晶硅层（20）上。使用常规光刻（例如，深UV光刻）在BARC层（30）上形成抗蚀剂图案（40）。使用抗蚀剂图案（40）用HBr / O 2的蚀刻化学品蚀刻BARC层（30），直到检测到端点。然后使用在BARC和抗蚀剂之间具有大约一对一的选择性的相同蚀刻化学品来对BARC层（30）和抗蚀剂图案（40）进行过蚀刻。过蚀刻是控制抗蚀剂/ BARC图案中线宽降低的定时蚀刻。图案（50）的最小尺寸减小到低于光刻工具的实际分辨率极限。最后，使用减小的宽度图案（50）蚀刻多晶硅层（20）。

33. 发明授权

US08785149B2 In vitro cellular bioassay for neurotoxicity testing 有权
标题翻译：用于神经毒性试验的体外细胞生物测定
公开(公告)号：US08785149B2
公开(公告)日：2014-07-22
申请号：US13639541
申请日：2011-04-08
申请人： Linda L. Restifo , Robert Kraft
发明人： Linda L. Restifo , Robert Kraft
IPC分类号： C12Q1/18
CPC分类号： C12Q1/025 , G01N33/5058
摘要： The present invention provides neurotoxicity and developmental neurotoxicity screening methods employing primary cultured neurons from Drosophila.
摘要翻译：本发明提供了使用来自果蝇的原代培养神经元的神经毒性和发育性神经毒性筛选方法。

34. 发明授权

US08558752B2 Variable pitch mandrel wound antennas and systems and methods of making same 失效
标题翻译：可变节距心轴缠绕天线及其制造方法
公开(公告)号：US08558752B2
公开(公告)日：2013-10-15
申请号：US12950636
申请日：2010-11-19
申请人： Paul Amadeo , Jose Flores , Robert Kraft
发明人： Paul Amadeo , Jose Flores , Robert Kraft
IPC分类号： H01Q21/00
CPC分类号： H01Q7/00 , G06K19/07779 , G06K19/07781 , H01F41/074 , H01F41/098 , H01Q1/2225 , Y10T29/49016
摘要： A system and method for fabricating a mandrel wound antenna are provided. The method includes securing a first end of a wire to a first portion of a mandrel tool, where the mandrel tool includes a faceplate supporting a plurality of posts, and the posts arranged and disposed to define non-overlapping circumferential patterns. The method also includes wrapping the wire around outer peripheries of the plurality of posts to form non-overlapping wire coils around the plurality of circumferential patterns to provide an antenna. The method further includes securing a second end of the wire to a second portion of the mandrel tool, cutting the wire in proximity to the second end, attaching the antenna to a substrate separate from the faceplate, and detaching the antenna from the faceplate.
摘要翻译：提供了一种用于制造心轴缠绕天线的系统和方法。该方法包括将线的第一端固定到心轴工具的第一部分，其中心轴工具包括支撑多个柱的面板，以及布置和设置以限定非重叠圆周图案的柱。该方法还包括围绕多个柱的外周缠绕线以在多个圆周图案周围形成不重叠的线圈以提供天线。该方法还包括将线的第二端固定到心轴工具的第二部分，将线接近第二端切割，将天线连接到与面板分离的基底，以及将天线从面板上分离。

35. 发明授权

US08348171B2 Smartcard interconnect 失效
标题翻译：智能卡互连
公开(公告)号：US08348171B2
公开(公告)日：2013-01-08
申请号：US13030993
申请日：2011-02-18
申请人： Paul Amadeo , Jose Flores , Robert Kraft
发明人： Paul Amadeo , Jose Flores , Robert Kraft
IPC分类号： G06K19/06
CPC分类号： G06K19/07749 , G06K19/07752 , G06K19/07779 , G06K19/07781 , Y10T29/49162
摘要： A smart card inlay and method for assembling the same are provided. The method includes attaching a first trace to a substrate, attaching a second trace to the substrate, attaching an antenna wire to the substrate, coupling a first end of the antenna wire to a first area of the first trace, and coupling a second end of the antenna wire to a first area of the second trace. A second area of the first trace and a second area of the second trace are configured to be coupled to an integrated circuit (IC) or IC module, and the first area of the first trace is located away from the second area of the first trace and the first area of the second trace is located away from the second area of the second trace.
摘要翻译：提供了一种用于组装智能卡嵌体和方法。该方法包括将第一迹线附接到衬底，将第二迹线附接到衬底，将天线连接到衬底，将天线线的第一端耦合到第一迹线的第一区域，以及将第天线连接到第二迹线的第一区域。第一迹线的第二区域和第二迹线的第二区域被配置为耦合到集成电路（IC）或IC模块，并且第一迹线的第一区域位于远离第一迹线的第二区域并且第二迹线的第一区域位于远离第二迹线的第二区域的位置。

36. 发明授权

US07985603B2 Ferroelectric capacitor manufacturing process 有权
标题翻译：铁电电容器制造工艺
公开(公告)号：US07985603B2
公开(公告)日：2011-07-26
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
IPC分类号： H01L21/00 , H01L21/02
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底上形成导电和铁电材料层。图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

37. 发明申请

US20080283975A1 FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE ETCH STOP DEPOSITION TO PROMOTE BETTER DIELECTRIC STACK ADHESION 有权
标题翻译：在碳化硅蚀刻停止沉积期间形成硅氧化物界面层以促进更好的电介质粘结
公开(公告)号：US20080283975A1
公开(公告)日：2008-11-20
申请号：US11750669
申请日：2007-05-18
申请人： Laura M. Matz , Ting Y. Tsui , Thad E. Briggs , Robert Kraft
发明人： Laura M. Matz , Ting Y. Tsui , Thad E. Briggs , Robert Kraft
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L21/3148 , H01L21/02126 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31608 , H01L21/3185 , H01L21/76807 , H01L21/76832 , H01L21/76834
摘要： In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.
摘要翻译：根据本教导，提供半导体器件以及在集成电路中制造半导体器件和电介质叠层的方法。在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构，并在第一处理室中在半导体结构之上形成蚀刻停止层。该方法还可以包括在第一处理室中的蚀刻停止层之上形成薄的氧化硅层，并在第二处理室中的薄氧化硅层上形成超低k电介质层，其中形成薄氧化硅层改善与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质堆叠相比，蚀刻停止层和超低k电介质之间的粘附性。

38. 发明授权

US07300883B2 Method for patterning sub-lithographic features in semiconductor manufacturing 有权
标题翻译：在半导体制造中图案化亚光刻特征的方法
公开(公告)号：US07300883B2
公开(公告)日：2007-11-27
申请号：US10930228
申请日：2004-08-31
申请人： Francis G. Celii , Brian A. Smith , James Blatchford , Robert Kraft
发明人： Francis G. Celii , Brian A. Smith , James Blatchford , Robert Kraft
IPC分类号： H01L21/336 , H01L21/302 , H01L21/461 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of forming a gate electrode (24′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask. The hardmask layer elements (26′) then mask the etch of the underlying polysilicon layer (24), to define the gate electrodes (24′), having gate widths that are narrower than the minimum dimension available through photolithography.
摘要翻译：公开了一种形成用于金属氧化物半导体（MOS）集成电路的栅电极（24'）的方法。例如由富含硅的氮化物形成的硬掩模层（26）沉积在要形成栅电极（24'）的多晶硅层（24）上。然后在硬掩模层（26）上形成抗反射涂层或底部抗反射涂层或BARC层（29），光刻图案化光致抗蚀剂（30）以限定栅电极（24'）的图案，，尽管对于更宽的光刻宽度（LW）。图案从光致抗蚀剂（30）转移到BARC层（29）。然后将BARC层（29）的其余元件优选地通过定时各向同性蚀刻修整到亚光刻宽度（SW）。然后通过该层的各向异性蚀刻，使用修剪的BARC元件（29）作为掩模将该图案转移到硬掩模层（26）。硬掩模层元件（26'）然后掩蔽下面的多晶硅层（24）的蚀刻，以限定栅电极（24'），栅极宽度比通过光刻可用的最小尺寸窄。

39. 发明申请

US20060046498A1 Method for patterning sub-lithographic features in semiconductor manufacturing 有权
标题翻译：在半导体制造中图案化亚光刻特征的方法
公开(公告)号：US20060046498A1
公开(公告)日：2006-03-02
申请号：US10930228
申请日：2004-08-31
申请人： Francis Celii , Brian Smith , James Blatchford , Robert Kraft
发明人： Francis Celii , Brian Smith , James Blatchford , Robert Kraft
IPC分类号： H01L21/00
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of forming a gate electrode (24′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask. The hardmask layer elements (26′) then mask the etch of the underlying polysilicon layer (24), to define the gate electrodes (24′), having gate widths that are narrower than the minimum dimension available through photolithography.
摘要翻译：公开了一种形成用于金属氧化物半导体（MOS）集成电路的栅电极（24'）的方法。例如由富含硅的氮化物形成的硬掩模层（26）沉积在要形成栅电极（24'）的多晶硅层（24）上。然后在硬掩模层（26）上形成抗反射涂层或底部抗反射涂层或BARC层（29），光刻图案化光致抗蚀剂（30）以限定栅电极（24'）的图案，，尽管对于更宽的光刻宽度（LW）。图案从光致抗蚀剂（30）转移到BARC层（29）。然后将BARC层（29）的其余元件优选地通过定时各向同性蚀刻修整到亚光刻宽度（SW）。然后通过该层的各向异性蚀刻，使用修剪的BARC元件（29）作为掩模将该图案转移到硬掩模层（26）。硬掩模层元件（26'）然后掩蔽下面的多晶硅层（24）的蚀刻，以限定栅电极（24'），栅极宽度比通过光刻可用的最小尺寸窄。

40. 发明申请

US20050103022A1 Methods and apparatus for operating gas turbine engines 失效
标题翻译：运行燃气轮机的方法和装置
公开(公告)号：US20050103022A1
公开(公告)日：2005-05-19
申请号：US10929910
申请日：2004-08-30
申请人： Robert Kraft
发明人： Robert Kraft
IPC分类号： F02C5/02 , F02K3/08 , F02K7/02 , F02K7/075 , F23C15/00 , F23R7/00 , F02C5/00
CPC分类号： F23C15/00 , F02C5/02 , F02K3/08 , F02K7/02 , F02K7/075 , F05D2270/11 , F23R7/00 , Y02T50/671
摘要： A method for operating a pulse detonation system. The method includes providing a pulse detonation chamber including a plurality of detonation tubes extending therein, and detonating a mixture of fuel and air within each detonation tube such that at least a first tube is detonated at a different time than at least a second detonation tube.
摘要翻译：一种操作脉冲爆震系统的方法。该方法包括提供脉冲爆震室，其包括在其中延伸的多个爆管，并且在每个爆管内引爆燃料和空气的混合物，使得至少第一管在不同于至少第二爆管的时间内被引爆。

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