专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070298521A1 METHOD FOR CLEANING POST-ETCH NOBLE METAL RESIDUES 有权
标题翻译：清除后处理金属残留物的方法
公开(公告)号：US20070298521A1
公开(公告)日：2007-12-27
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/00
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译：提出了制造半导体器件的方法。一方面，该方法包括在半导体衬底上形成导电和铁电材料层。图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

2. 发明申请

US20090194801A1 FERROELECTRIC CAPACITOR MANUFACTURING PROCESS 有权
标题翻译：电磁电容器制造工艺
公开(公告)号：US20090194801A1
公开(公告)日：2009-08-06
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
IPC分类号： H01L27/00 , H01L21/00
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底上形成导电和铁电材料层。图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

3. 发明授权

US07723199B2 Method for cleaning post-etch noble metal residues 有权
标题翻译：蚀刻后贵金属残留物的方法
公开(公告)号：US07723199B2
公开(公告)日：2010-05-25
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/02
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译：提出了制造半导体器件的方法。一方面，该方法包括在半导体衬底上形成导电和铁电材料层。图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

4. 发明授权

US07985603B2 Ferroelectric capacitor manufacturing process 有权
标题翻译：铁电电容器制造工艺
公开(公告)号：US07985603B2
公开(公告)日：2011-07-26
申请号：US12025207
申请日：2008-02-04
申请人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , Robert Kraft , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Theodore S. Moise
IPC分类号： H01L21/00 , H01L21/02
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.
摘要翻译：一种制造半导体器件的方法。该方法包括在半导体衬底上形成导电和铁电材料层。图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

5. 发明授权

US08093070B2 Method for leakage reduction in fabrication of high-density FRAM arrays 有权
标题翻译：高密度FRAM阵列制造中泄漏减少的方法
公开(公告)号：US08093070B2
公开(公告)日：2012-01-10
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译：提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用第二次灰化过程。

6. 发明申请

US20080081380A1 Method for leakage reduction in fabrication of high-density FRAM arrays 有权
标题翻译：高密度FRAM阵列制造中泄漏减少的方法
公开(公告)号：US20080081380A1
公开(公告)日：2008-04-03
申请号：US11706722
申请日：2007-02-15
申请人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
发明人： Francis Gabriel Celii , Kezhakkedath R. Udayakumar , Gregory B. Shinn , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L21/00
CPC分类号： H01L28/75 , H01L27/11507 , H01L28/55
摘要： A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
摘要翻译：提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用第二次灰化过程。

7. 发明授权

US06841396B2 VIA0 etch process for FRAM integration 有权
标题翻译：用于FRAM集成的VIA0蚀刻工艺
公开(公告)号：US06841396B2
公开(公告)日：2005-01-11
申请号：US10440697
申请日：2003-05-19
申请人： Francis Gabriel Celii , K. R. Udayakumar , Scott R. Summerfelt , Theodore S. Moise
发明人： Francis Gabriel Celii , K. R. Udayakumar , Scott R. Summerfelt , Theodore S. Moise
IPC分类号： H01L21/00 , H01L21/20 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.
摘要翻译：铁电存储器件包括逻辑可编程电容参考电路。电路适于在感测操作模式期间产生参考电压，其中参考电压包括作为一个以上存储器条件的函数的值。存储器件还包括位线对，其中位线对的第一位线具有耦合的铁电电容器用于感测位线对，并且位线对的第二位线耦合到参考电压。感测电路耦合到位线对，并且被配置为使用与第一位线相关联的电压和第二位线上的参考电压来检测与铁电电容器相关联的数据状态。

8. 发明授权

US07183602B2 Ferroelectric capacitor hydrogen barriers and methods for fabricating the same 有权
标题翻译：铁电电容器氢屏障及其制造方法
公开(公告)号：US07183602B2
公开(公告)日：2007-02-27
申请号：US11033224
申请日：2005-01-11
申请人： K. R. Udayakumar , Theodore S. Moise , Scott R. Summerfelt
发明人： K. R. Udayakumar , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/11507 , H01L28/57
摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.
摘要翻译：提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117）氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

9. 发明授权

US06686210B1 Methods for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity 有权
标题翻译：用各向异性铁电极化或介电常数控制薄膜晶体结构的方法
公开(公告)号：US06686210B1
公开(公告)日：2004-02-03
申请号：US09349439
申请日：1999-07-09
申请人： Stephen R. Gilbert , Theodore S. Moise , Scott R. Summerfelt
发明人： Stephen R. Gilbert , Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L2100
CPC分类号： H01L28/55 , C23C16/40 , C23C16/409 , C23C16/44 , C23C16/517 , H01L21/31604 , H01L21/31691 , H01L27/0629 , H01L27/0805 , H01L28/60
摘要： A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment resulting in a texture with higher ferroelectric polarization or permittivity which is normally energetically disfavored.
摘要翻译：通过离子轰击来控制具有各向异性铁电极化或介电常数的薄膜的晶体结构的方法，导致通常在能量上不利的铁电极化或介电常数较高的纹理。

10. 发明授权

US5905272A Optical receiver 失效
标题翻译：光接收机
公开(公告)号：US5905272A
公开(公告)日：1999-05-18
申请号：US960988
申请日：1997-10-30
申请人： Theodore S. Moise
发明人： Theodore S. Moise
IPC分类号： H01L27/144 , H01L31/08 , H01L29/06
CPC分类号： B82Y10/00 , H01L27/144 , H01L31/08
摘要： Apparatus for optical communications (10, 110, 210) includes a low-temperature grown photoconductor (12, 140, 220) coupled to at least one resonant tunneling device (14, 120, 130, 230, 240). When exposed to an input light, low-temperature grown photoconductor (10, 110, 210) absorbs photons, which decreases the resistivity, and thus the resistance of the photoconductor. This decrease in resistance causes a decrease in the voltage drop across photoconductor (12, 140, 220), which causes a corresponding increase in the voltage drop across resonant tunneling device (14, 120, 130, 230, 140).
摘要翻译：用于光通信的装置（10,110,210）包括耦合到至少一个谐振隧穿装置（14,120,130,230,240）的低温生长的光电导体（12,140,220）。当暴露于输入光时，低温生长的光电导体（10,110,210）吸收光子，这降低了电阻率，并因此降低了光电导体的电阻。电阻的这种降低导致光电导体（12,140,220）上的电压降的降低，这导致谐振隧穿装置（14,120,130,230,140）上的电压降的相应增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式