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31. 发明授权

US06331730B1 Push-in type semiconductor device including heat spreader 有权
标题翻译：包括散热器的推入式半导体器件
公开(公告)号：US06331730B1
公开(公告)日：2001-12-18
申请号：US09296466
申请日：1999-04-22
申请人： Takeshi Terasaki , Hideo Miura , Chikara Nakajima , Makoto Kitano
发明人： Takeshi Terasaki , Hideo Miura , Chikara Nakajima , Makoto Kitano
IPC分类号： H02K1936
CPC分类号： H01L24/01 , H01L23/049 , H01L23/3121 , H01L24/33 , H01L2224/83385 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/18301 , H01L2924/3512 , H01L2924/00 , H01L2924/00012
摘要： A push-in type semiconductor chip has a semiconductor device, a support electrode body bonded to one of the end portions of the semiconductor chip and supported by, and fixed to, a heat spreader at a support fixing portion thereof, a lead electrode body bonded to the other end portion of the semiconductor chip and an insulating/sealing member disposed at the bond portion between the semiconductor chip and the support electrode body and at the bond portion between the semiconductor chip and the lead electrode body. The support electrode body includes a first portion having an outer diameter different from that of the support fixing portion at which the support electrode body is supported and fixed by the heat spreader. By setting a predetermined relationship between the outer diameters of the first portion and the support fixing portion, deformation and breakage of the semiconductor chip during assembly can be prevented.
摘要翻译：推入型半导体芯片具有半导体器件，支撑电极体，其结合到半导体芯片的一个端部并由其支撑固定部分上的散热器支撑并固定到其上，引线电极体接合到半导体芯片的另一端部以及设置在半导体芯片和支撑电极体之间的接合部以及半导体芯片和引线电极体的接合部的绝缘/密封构件。支撑电极体包括具有与支撑固定部分不同的外径的第一部分，支撑电极主体由散热器支撑和固定。通过设置第一部分的外径和支撑固定部分之间的预定关系，可以防止组装期间半导体芯片的变形和断裂。

32. 发明授权

US06646350B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06646350B2
公开(公告)日：2003-11-11
申请号：US09922230
申请日：2001-08-03
申请人： Naotaka Tanaka , Hideo Miura , Yoshiyuki Kado , Ikuo Yoshida , Takahiro Naito
发明人： Naotaka Tanaka , Hideo Miura , Yoshiyuki Kado , Ikuo Yoshida , Takahiro Naito
IPC分类号： H01L2352
CPC分类号： H01L23/562 , H01L21/563 , H01L23/145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/12044 , H01L2924/00
摘要： In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a thermal expansion coefficient of an adhesive (3) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion (6) is in the range of 5 to 10 GPa. Further, the build-up portion (6) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C. By setting or selecting the physical properties in the manner disclosed above, it is possible to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric bonding between the bump pads (2) formed on the LSI chips (1) and the electrode pads (4) on the interconnection substrate (5) within an guaranteed temperature range.
摘要翻译：为了实现能够保持高可靠性的半导体器件及其制造方法，在形成在LSI芯片上的每个凸块焊盘和形成在互连基板上的每个电极焊盘之间的电连接在保证的温度范围内，粘合剂（3）的膨胀系数在20〜60ppm的范围内，积聚部（6）的弹性模量在5〜10GPa的范围内。此外，积存部（6）由多层积层基板构成，在该多层积层基板中，增益部分的损耗系数的峰值（玻璃化转变温度）存在于100℃〜 250℃，并且不存在于0℃至100℃的范围内。通过以上述方式设置或选择物理性质，可以实现可以保持的半导体器件及其制造方法在保证温度范围内，形成在LSI芯片（1）上的凸块焊盘（2）和互连基板（5）上的电极焊盘（4）之间的电连接具有高可靠性。

33. 发明申请

US20070187823A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070187823A1
公开(公告)日：2007-08-16
申请号：US11783983
申请日：2007-04-13
申请人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
发明人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/563 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/4807 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/4851 , H01L2224/48624 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85205 , H01L2225/06558 , H01L2225/06568 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20751 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00015
摘要： An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
摘要翻译：本发明的目的在于，对于具有Cu互连/ Low-k材料的堆叠互连结构的LSI，可以实现能够减少对焊盘的损伤的窄间距引线接合技术和类似于传统LSI的铝互连。在具有由Cu互连/ Low-k电介质材料制成的多层互连的半导体器件中，上述目的可以通过一种焊盘结构来实现，其中所有的布线层直到最上盖互连件都是由Cu 布线层和由Cu层形成的接合焊盘部分在Cu层上装有诸如Ti（钛）膜（钨）的耐火材料中间金属层和中间金属层上的铝合金层。

34. 发明申请

US20050001314A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050001314A1
公开(公告)日：2005-01-06
申请号：US10873251
申请日：2004-06-23
申请人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
发明人： Naotaka Tanaka , Tomio Iwasaki , Hideo Miura , Yasuyuki Nakajima , Tomoo Matsuzawa
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/44 , H01L21/56 , H01L21/60 , H01L21/768 , H01L23/31 , H01L23/48 , H01L23/485 , H01L23/532 , H01L25/065
CPC分类号： H01L23/53238 , H01L21/563 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/4807 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48453 , H01L2224/48465 , H01L2224/4851 , H01L2224/48624 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85205 , H01L2225/06558 , H01L2225/06568 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01105 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20751 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2924/00015
摘要： An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
摘要翻译：本发明的目的在于，对于具有Cu互连/ Low-k材料的堆叠互连结构的LSI，可以实现能够减少对焊盘的损伤的窄间距引线接合技术和类似于常规LSI的铝互连。在具有由Cu互连/ Low-k电介质材料制成的多层互连的半导体器件中，上述目的可以通过一种焊盘结构来实现，其中所有的布线层直到最上盖互连件都是由Cu 布线层和由Cu层形成的接合焊盘部分在Cu层上装有诸如Ti（钛）膜（钨）的耐火材料中间金属层和中间金属层上的铝合金层。

35. 发明授权

US07241685B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07241685B2
公开(公告)日：2007-07-10
申请号：US10390413
申请日：2003-03-18
申请人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shinji Nishihara , Masashi Sahara
发明人： Hiroshi Moriya , Tomio Iwasaki , Hideo Miura , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L21/44
CPC分类号： H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.
摘要翻译：提供一种具有降低短路可能性的布线结构的半导体器件及其制造方法。此外，提供了具有高可靠性的半导体器件。此外，提供了一种具有高产率的半导体器件。在半导体衬底的一个主表面侧形成布线，并且具有相邻导体层和主布线层的叠层结构。主配线层包含一个添加的元素以防止迁移。相邻的导体层由用于防止主要构成元素和主配线层的添加元素扩散到相邻导体层下方的基板中的材料形成，并且添加元素在靠近界面处的位置的浓度与相邻的导体层间隔开的主配线层的添加元素的浓度相比，相邻的导体层和主布线层的电位低。

36. 发明申请

US20070140617A1 Optical device having connections with optical members through protective medium 有权
标题翻译：光学装置通过保护介质与光学构件连接
公开(公告)号：US20070140617A1
公开(公告)日：2007-06-21
申请号：US11591560
申请日：2006-11-02
申请人： Shinichi Shimotsu , Shinichiro Sonoda , Hideo Miura
发明人： Shinichi Shimotsu , Shinichiro Sonoda , Hideo Miura
IPC分类号： G02B6/32 , G02B6/26 , G02B6/42
CPC分类号： G02B6/262 , G02B6/32 , G02B6/421
摘要： An optical device includes: a first optical member having a light-exit end at which light exits the first optical member; a second optical member having a light-entrance end which abuts the light-exit end through a protective medium and from which the light enters the second optical member; and the protective medium which is arranged between the light-exit end and the light-entrance end, and suppresses fixing together of the light-exit end and the light-entrance end. Specifically, the protective medium is transparent and arranged between the light-exit end and the light-entrance end, and is reusable even after the light-exit end and the light-entrance end are pressed together with a pressure of approximately 0.5 or 1 kgf and are then separated from each other.
摘要翻译：光学装置包括：具有光出射端的第一光学构件，光从该第一光学构件出射; 第二光学构件，其具有通过保护介质邻接所述光出射端的光入射端，并且所述光进入所述第二光学构件; 以及布置在光出射端和光入射端之间的保护介质，并且抑制光出射端和光入射端的固定在一起。具体地说，保护介质是透明的并且设置在光出射端和光入射端之间，并且即使在光出射端和光入射端之间也以约0.5或1kgf的压力被压在一起然后彼此分离。

37. 发明授权

US07217971B2 Miniaturized semiconductor device with improved dielectric properties 有权
标题翻译：具有改善介电特性的小型半导体器件
公开(公告)号：US07217971B2
公开(公告)日：2007-05-15
申请号：US10848473
申请日：2004-05-17
申请人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
发明人： Tomio Iwasaki , Hiroshi Moriya , Hideo Miura , Shuji Ikeda
IPC分类号： H01L31/119
CPC分类号： H01L21/823462 , H01L21/28097 , H01L21/28185 , H01L21/28194 , H01L21/28518 , H01L21/31604 , H01L21/823412 , H01L27/1085 , H01L27/10873 , H01L29/045 , H01L29/4908 , H01L29/4975 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/78696
摘要： Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.
摘要翻译：在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8,9，以便成为MOS晶体管。氧化锆或氧化铪被用作栅介质膜6,7的主要成分。栅介质膜6,7例如通过CVD形成。作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用表面为（111）晶面的基板的情况下，在使用表面为（001）晶面的硅基板的情况下，氧的扩散系数小于1/100，氧气扩散被控制。因此，控制氧扩散，防止漏电流的产生，提高性能。实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

38. 发明授权

US06949387B2 Method of designing a semiconductor device 失效
标题翻译：设计半导体器件的方法
公开(公告)号：US06949387B2
公开(公告)日：2005-09-27
申请号：US10626718
申请日：2003-07-25
申请人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L21/66
CPC分类号： H01L21/76205 , H01L21/76202 , H01L27/0802
摘要： A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.
摘要翻译：提供了一种半导体器件的技术，其包括在器件形成区域上形成电路区域和半导体衬底上的器件隔离区域，器件隔离区域的宽度与其相邻电路区域的宽度的比率被设置为2至还提供了一种设计方法，包括进行测量，例如衬垫氧化膜和氮化物膜的厚度，氮化物膜的内部应力，器件形成和隔离区域的宽度，蚀刻部分的深度的用于在器件隔离区域中形成沟槽的氮化物膜，由于热氧化而在沟槽附近进行导电应力分析，以及与器件形成区域的宽度和不引导的器件隔离区域的设定值发生脱位。

39. 发明授权

US06882665B2 Light wavelength converting module 失效
标题翻译：光波长转换模块
公开(公告)号：US06882665B2
公开(公告)日：2005-04-19
申请号：US09972960
申请日：2001-10-10
申请人： Hideo Miura , Shinichiro Sonoda
发明人： Hideo Miura , Shinichiro Sonoda
IPC分类号： H01S5/024 , H01S5/0683 , H01S3/10 , H01S3/30
CPC分类号： H01S5/02415 , H01S5/0683
摘要： A light wavelength converting module is provided in which generation of noise due to return light is prevented and a wave whose wavelength is converted can be obtained stably. The light wavelength converting module is formed by a semiconductor laser from which a fundamental wave exits, and a light wavelength converting element which is optically coupled to the semiconductor laser and which converts a wavelength of the fundamental wave which enters from the semiconductor laser. A wavelength plate is disposed at a light exiting side of the light wavelength converting element. An IR cutting filter, which serves as a removing means for removing the fundamental wave from a second harmonic, is disposed between the wavelength plate and the light wavelength converting element.
摘要翻译：提供一种光波长转换模块，其中防止了由返回光产生的噪声，并且可以稳定地获得波长转换的波。光波长转换模块由基波出射的半导体激光器和与半导体激光器光学耦合并转换从半导体激光器入射的基波的波长的光波长转换元件形成。波长板设置在光波长转换元件的光出射侧。作为用于从二次谐波除去基波的去除装置的红外截止滤光器设置在波长板和光波长转换元件之间。

40. 发明授权

US06858515B2 Process for producing semiconductor device and semiconductor device produced thereby 失效
标题翻译：由此生产半导体器件和半导体器件的方法
公开(公告)号：US06858515B2
公开(公告)日：2005-02-22
申请号：US10638485
申请日：2003-08-12
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Kozo Watanabe , Kenji Kanamitsu
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L29/06
CPC分类号： H01L21/76232 , H01L29/0657
摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.
摘要翻译：在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

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