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31. 发明授权

US07732798B2 Programmable via structure for three dimensional integration technology 有权
标题翻译：可编程通孔结构，用于三维集成技术
公开(公告)号：US07732798B2
公开(公告)日：2010-06-08
申请号：US12178921
申请日：2008-07-24
申请人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Chung Hon Lam , Dennis M. Newns , Matthew R. Wordeman , Albert M. Young
发明人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Chung Hon Lam , Dennis M. Newns , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , H01L23/5226 , H01L23/5252 , H01L23/5256 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1286 , H01L2924/0002 , H01L2924/00
摘要： A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.
摘要翻译：用于三维积分（3DI）半导体器件的可编程链路结构包括至少部分地填充有相变材料（PCM）和靠近PCM的加热装置的通孔。加热装置被配置为将PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态。因此，通路限定位于其一端的输入连接与位于其另一端的输出连接之间的可编程连接。

32. 发明授权

US07521950B2 Wafer level I/O test and repair enabled by I/O layer 失效
标题翻译：通过I / O层启用晶圆级I / O测试和修复
公开(公告)号：US07521950B2
公开(公告)日：2009-04-21
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/00 , G01N37/00 , G06F13/20 , G06F13/36 , G06F11/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

33. 发明申请

US20090072213A1 Programmable Via Structure for Three Dimensional Integration Technology 有权
标题翻译：可编程通道结构三维集成技术
公开(公告)号：US20090072213A1
公开(公告)日：2009-03-19
申请号：US12178921
申请日：2008-07-24
申请人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Chung Hon Lam , Dennis M. Newns , Matthew R. Wordeman , Albert M. Young
发明人： Bruce G. Elmegreen , Lia Krusin-Elbaum , Chung Hon Lam , Dennis M. Newns , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , H01L23/5226 , H01L23/5252 , H01L23/5256 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1286 , H01L2924/0002 , H01L2924/00
摘要： A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof
摘要翻译：用于三维积分（3DI）半导体器件的可编程链路结构包括至少部分地填充有相变材料（PCM）和靠近PCM的加热装置的通孔。加热装置被配置为将PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态。因此，通路限定位于其一端的输入连接与位于其另一端的输出连接之间的可编程连接

34. 发明授权

US06396298B1 Active feedback pulsed measurement method 失效
标题翻译：主动反馈脉冲测量方法
公开(公告)号：US06396298B1
公开(公告)日：2002-05-28
申请号：US09549503
申请日：2000-04-14
申请人： Albert M. Young , Samuel S. Osofsky
发明人： Albert M. Young , Samuel S. Osofsky
IPC分类号： G01R3126
CPC分类号： G01R31/2621 , G01R27/28
摘要： A pulse measurement method is applied to test devices such as high power FET transistors for measuring DC device parameters as well as for measuring S parameters during AC testing. The method uses an input gate bias tee for applying an accurately shaped pulsed input, a sensing bias tee for sensing terminal voltages, such as drain voltages for an FET, and a drive bias tee for coupling in a feedback signal provided by an active feedback circuit receiving AC coupled input error signal of the DC terminal voltage and for providing a drive signal as an error signal so as to maintain the applied DC test voltages at stable levels for improved accuracy.
摘要翻译：应用脉冲测量方法来测试诸如大功率FET晶体管的器件，用于测量DC器件参数以及在AC测试期间测量S参数。该方法使用用于施加精确成形的脉冲输入的输入栅极偏置T形件，用于感测端子电压的感测偏置T形，例如用于FET的漏极电压，以及用于在由有源反馈电路提供的反馈信号中耦合的驱动偏置三通接收直流端电压的交流耦合输入误差信号，并提供驱动信号作为误差信号，以便将所施加的直流测试电压保持在稳定水平以提高精度。

35. 发明授权

US08174841B2 Adaptive interconnect structure 失效
标题翻译：自适应互连结构
公开(公告)号：US08174841B2
公开(公告)日：2012-05-08
申请号：US12430416
申请日：2009-04-27
申请人： Leland Chang , Matthew R. Wordeman , Albert M. Young
发明人： Leland Chang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01R43/00
CPC分类号： H01L25/0657 , H01L23/5252 , H01L23/5256 , H01L24/06 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/05555 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/014 , H01L2924/04953 , H01L2924/00014
摘要： An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
摘要翻译：半导体结构上的接触焊盘阵列的间距小于用于垂直堆叠半导体结构的接合工艺的覆盖公差的两倍。用于匹配接触针的覆盖变化区域内的一组接触焊盘可以电连接到可编程触点阵列，使得一个可编程触点连接到覆盖变化区域内的每个接触焊盘。一个接触垫可以设置有多个可编程触点。在半导体结构堆叠之后，通过连接或断开可编程触点来容纳接触引脚和接触焊盘之间的接触的可变性。由于接触引脚阵列的间距可能小于接合过程的覆盖变化的两倍，所以垂直堆叠结构中提供了高密度的互连。

36. 发明授权

US07999377B2 Method and structure for optimizing yield of 3-D chip manufacture 有权
标题翻译：优化3-D芯片制造产量的方法和结构
公开(公告)号：US07999377B2
公开(公告)日：2011-08-16
申请号：US12029122
申请日：2008-02-11
申请人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
发明人： Edward M. DeMulder , Sarah H. Knickerbocker , Michael J. Shapiro , Albert M. Young
IPC分类号： H01L23/488
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/13
摘要： The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.
摘要翻译：该过程开始于具有互补芯片的单独的器件晶片。薄金属捕获垫具有约10微米的优选厚度，使得在处理过程中可能施加大的压力而不损坏捕获垫，沉积在两个器件晶片上，然后对其进行测试和映射以获得良好的芯片位置。处理晶片连接到一个器件晶片，然后可以通过蚀刻和填充来减薄其改进。捕获垫被去除并在变薄后更换。切割具有处理晶片的器件晶片，并且将具有切割手柄晶片的附接部分的良好芯片定位并结合到另一器件晶片的良好芯片位置，并移除处理晶片部分。具有已知良好3-D芯片的器件晶片然后进行最终处理。

37. 发明授权

US07888164B2 Programmable via structure and method of fabricating same 有权
标题翻译：可编程通孔结构及其制造方法
公开(公告)号：US07888164B2
公开(公告)日：2011-02-15
申请号：US12538120
申请日：2009-08-08
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
IPC分类号： H01L21/02
CPC分类号： H01L45/122 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method of fabricating a programmable via structure is provided. The method includes providing a patterned heating material on a surface of an oxide layer. The oxide layer is located above a semiconductor substrate. A patterned dielectric material is formed having a least one via on a surface of the patterned heating material. The at least one via is filled with a phase change material such that a lower surface of the phase change material is in direct contact with a portion of the patterned heating material. A patterned diffusion barrier is formed on an exposed surface of the at least one via filled with the phase change material. A method of programmable a programmable via structure made by the method is also disclosed.
摘要翻译：提供一种制造可编程通孔结构的方法。该方法包括在氧化物层的表面上提供图案化的加热材料。氧化物层位于半导体衬底之上。在图案化加热材料的表面上形成具有至少一个通孔的图案化电介质材料。至少一个通孔填充有相变材料，使得相变材料的下表面与图案化加热材料的一部分直接接触。图案化的扩散阻挡层形成在填充有相变材料的至少一个通孔的暴露表面上。还公开了一种通过该方法制成的可编程通孔结构的方法。

38. 发明授权

US07847597B1 Precision frequency change detector 有权
标题翻译：精密变频检测器
公开(公告)号：US07847597B1
公开(公告)日：2010-12-07
申请号：US12456287
申请日：2009-06-15
申请人： Yat C. Chan , James C. Camparo , Walter A. Johnson , Christine Humphries, legal representative , Albert M. Young , Sarunas K. Karuza
发明人： Yat C. Chan , James C. Camparo , Walter A. Johnson , Albert M. Young , Sarunas K. Karuza
IPC分类号： G01R23/02 , H03D3/00 , H03K9/06
CPC分类号： G01R29/26 , G01R23/00 , G01R23/14 , G01R25/00
摘要： A frequency change detector splits a frequency standard signal into two undelayed frequency signals, one of which is delayed by a predetermined amount. The delayed signal is then mixed with the undelayed frequency signal into a mixed signal that is further filtered and amplified for providing an output signal indicating frequency changes of the frequency standard signal. The mixed frequency signal indicates frequency changes of the original frequency standard signal without reference to another frequency standard. This frequency change detector is well suited for use on satellites as an early warning detection of changes in on-board atomic frequency standards.
摘要翻译：频率变化检测器将频率标准信号分成两个未延迟的频率信号，其中一个延迟了预定的量。然后将延迟的信号与未延迟的频率信号混合成混合信号，该混合信号被进一步滤波和放大，以提供指示频率标准信号的频率变化的输出信号。混频信号表示原频率标准信号的频率变化，不参考另一频率标准。该频率变化检测器非常适合用于卫星，作为车载原子频率标准变化的早期预警检测。

39. 发明授权

US07786596B2 Hermetic seal and reliable bonding structures for 3D applications 有权
公开(公告)号：US07786596B2
公开(公告)日：2010-08-31
申请号：US12038501
申请日：2008-02-27
申请人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
发明人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

40. 发明申请

US20090140404A1 HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS 有权
标题翻译：用于3D应用的HERMETIC SEAL和可靠的结合结构
公开(公告)号：US20090140404A1
公开(公告)日：2009-06-04
申请号：US12038501
申请日：2008-02-27
申请人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
发明人： Kuan-Neng Chen , Bruce K. Furman , Edmund J. Sprogis , Anna W. Topol , Cornelia K. Tsang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L23/10
CPC分类号： H01L25/50 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.
摘要翻译：一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

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