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31. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

32. 发明授权

US06809043B1 Multi-stage, low deposition rate PECVD oxide 有权
标题翻译：多级，低沉积速率PECVD氧化物
公开(公告)号：US06809043B1
公开(公告)日：2004-10-26
申请号：US10173611
申请日：2002-06-19
申请人： Minh Van Ngo , Robert A. Huertas , Hieu Pham
发明人： Minh Van Ngo , Robert A. Huertas , Hieu Pham
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28247 , H01L21/3144 , H01L21/3145 , H01L21/31612
摘要： A silicon oxide layer is deposited at a thickness of about 50 Å or less by a multi-stage method comprising depositing a sub-layer of silicon oxide in each stage by PECVD at a low deposition rate. Embodiments include depositing a silicon dioxide liner over a gate electrode in at least four stages, each stage comprising depositing a sub-layer at a thickness of 10 Å or less.
摘要翻译：氧化硅层通过多级方法沉积在大约等于或小于50埃的厚度，包括通过PECVD以低沉积速率在每个阶段沉积氧化硅的子层。实施例包括在至少四个阶段中在栅电极上沉积二氧化硅衬垫，每个阶段包括沉积厚度为或更小的子层。

33. 发明授权

US06770905B1 Implantation for the formation of CuX layer in an organic memory device 失效
标题翻译：用于在有机存储器件中形成CuX层的植入
公开(公告)号：US06770905B1
公开(公告)日：2004-08-03
申请号：US10314054
申请日：2002-12-05
申请人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
发明人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
IPC分类号： H01L2940
CPC分类号： H01L51/0037 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0043 , H01L51/0046 , H01L51/0048 , H01L51/0052 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semiconductor layer and CuX layer made by implantation of a Group VIB element.
摘要翻译：公开了一种具有通过注入制造的CuX层的有机存储单元。有机存储单元由两个电极组成，至少一个电极含有铜，两个电极之间具有可控导电介质。可控导电介质包含通过注入VIB族元素制成的有机半导体层和CuX层。

34. 发明授权

US06660634B1 Method of forming reliable capped copper interconnects 有权
标题翻译：形成可靠封盖铜互连的方法
公开(公告)号：US06660634B1
公开(公告)日：2003-12-09
申请号：US10291612
申请日：2002-11-12
申请人： Minh Van Ngo , Shekhar Pramanick , Takeshi Nogami
发明人： Minh Van Ngo , Shekhar Pramanick , Takeshi Nogami
IPC分类号： H01L2144
CPC分类号： H01L21/76862 , H01L21/76801 , H01L21/76877 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10S438/902 , Y10S438/906 , H01L2924/00
摘要： The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon. The diffusion barrier layer is then deposited on the copper silicide layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, then treating the exposed surface of the Cu/Cu alloy interconnect to form the copper silicide layer thereon, and depositing a silicon nitride diffusion barrier layer on the copper silicide layer.
摘要翻译：扩散阻挡层或覆盖层对Cu或Cu合金互连构件的粘附通过处理Cu或Cu合金互连构件的暴露表面而显着增强：（a）在等离子体条件下用氨和硅烷或二氯硅烷形成铜硅化物层; 或（b）与氨等离子体接触，然后与硅烷或二氯硅烷反应，在其上形成硅化铜层。然后将扩散阻挡层沉积在硅化铜层上。实施例包括电镀或化学镀Cu或Cu合金以填充介电中间层中的镶嵌开口，化学机械抛光，然后处理Cu / Cu合金互连的暴露表面以在其上形成硅化铜层，并沉积氮化硅扩散阻挡层在硅化铜层上。

35. 发明授权

US06660621B1 Method of forming ultra-shallow junctions in a semiconductor wafer with silicon layer deposited from a gas precursor to reduce silicon consumption during salicidation 失效
标题翻译：在具有从气体前体沉积的硅层的半导体晶片中形成超浅结的方法，以减少在水化过程中的硅消耗
公开(公告)号：US06660621B1
公开(公告)日：2003-12-09
申请号：US10163461
申请日：2002-06-07
申请人： Paul R. Besser , Minh Van Ngo
发明人： Paul R. Besser , Minh Van Ngo
IPC分类号： H01L213205
CPC分类号： H01L29/41783 , H01L21/28518 , H01L29/665
摘要： A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.
摘要翻译：在半导体晶片中形成超浅结的方法形成栅极和源极/漏极结，其在栅极和源极/漏极结上的第一金属硅化物区具有上表面。这些第一金属硅化物区域具有较高的电阻率。通过等离子体增强化学气相沉积（PECVD）将非晶硅沉积在第一金属硅化物区域上。 PECVD工艺可以是较低压力的沉积工艺，在多个工位上执行以在多层中形成非晶硅层。这就形成了跨越晶片的更均匀的非晶硅层和不同的图案化密度，从而提高了器件性能和特性。然后通过第一金属硅化物区域和通过PECVD工艺沉积的非晶硅的扩散反应，进行退火以形成较低电阻率的第二金属硅化物区域。

36. 发明授权

US06656763B1 Spin on polymers for organic memory devices 失效
标题翻译：旋转有机存储器件的聚合物
公开(公告)号：US06656763B1
公开(公告)日：2003-12-02
申请号：US10385375
申请日：2003-03-10
申请人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
发明人： Jane V. Oglesby , Christopher F. Lyons , Ramkumar Subramanian , Angela T. Hui , Minh Van Ngo , Suzette K. Pangrle
IPC分类号： H01L5140
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C2213/16 , G11C2213/71 , H01L27/285 , H01L51/0003 , H01L51/0004 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0038 , H01L51/0041 , H01L51/005 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0084 , H01L51/0085 , Y10S977/843 , Y10S977/944
摘要： A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin-on techniques with the assistance of certain solvents.
摘要翻译：公开了一种在两个电极之间制造具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。在某些溶剂的帮助下，使用旋转技术形成有机半导体层。

37. 发明授权

US06583051B2 Method of manufacturing an amorphized barrier layer for integrated circuit interconnects 失效
公开(公告)号：US06583051B2
公开(公告)日：2003-06-24
申请号：US09989972
申请日：2001-11-20
申请人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
发明人： Sergey D. Lopatin , Minh Van Ngo , Minh Quoc Tran
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76862 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

38. 发明授权

US06576548B1 Method of manufacturing a semiconductor device with reliable contacts/vias 有权
标题翻译：制造具有可靠接触/通孔的半导体器件的方法
公开(公告)号：US06576548B1
公开(公告)日：2003-06-10
申请号：US10079861
申请日：2002-02-22
申请人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
发明人： Amy Tu , Minh Van Ngo , Austin Frenkel , Robert J. Chiu , Jeff Erhardt
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/31105 , H01L21/76804 , H01L21/76846 , H01L21/76877
摘要： Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e.g., a silicon oxide derived from TEOS or BPSG, at an angle of about 83° to about 86°, depositing a thin layer of Ti, e.g., at a thickness of about 250 Å to about 350 Å, depositing at least one layer of titanium nitride, e.g., three layers of titanium nitride, at a total thickness of about 130 Å to about 170 Å, and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 Å/min to fill the opening.
摘要翻译：通过溅射蚀刻形成可靠的触点/通孔，以对形成在电介质层中的开口的暴露边缘进行曝光，沉积复合阻挡层，然后以低沉积速率用钨填充开口。所得到的接触/通孔显示出显着降低的孔隙率和接触电阻。实施例包括溅射蚀刻，以约83°至约86°的角度倾斜形成在氧化物电介质层中的开口的边缘，例如衍生自TEOS或BPSG的氧化硅，沉积Ti薄层，在约250埃至大约350埃的厚度上沉积至少一层氮化钛，例如三层氮化钛，总厚度为约至约为170埃，然后以沉积速率沉积钨约1,900至约2,300埃/分钟以填充开口。

39. 发明授权

US06548403B1 Silicon oxide liner for reduced nickel silicide bridging 有权
标题翻译：用于还原硅化镍桥接的氧化硅衬垫
公开(公告)号：US06548403B1
公开(公告)日：2003-04-15
申请号：US09679871
申请日：2000-10-05
申请人： Minh Van Ngo , Christy Mei-Chu Woo
发明人： Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L29/6659
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by forming a relatively thick silicon oxide liner on the side surfaces of the gate electrode and adjacent surface of the semiconductor substrate before forming the silicon nitride sidewall spacers thereon. Embodiments include forming a silicon dioxide liner at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers thereon.
摘要翻译：在形成氮化硅侧壁之前，通过在栅电极的侧表面和半导体衬底的相邻表面上形成相对较厚的氧化硅衬垫来防止在栅电极上的硅化镍层与氮化硅侧壁间隔物之间的源极/漏极区之间的桥接垫片。在形成氮化硅侧壁间隔物之前，实施例包括在大约至大约600埃的厚度形成二氧化硅衬垫。

40. 发明授权

US06492258B1 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY 有权
标题翻译：用于通过退火互连线和使用低偏置电压和低中间层介电沉积速率和半导体芯片制造来减少0.25微米和小型半导体芯片技术的应力诱发电位的方法
公开(公告)号：US06492258B1
公开(公告)日：2002-12-10
申请号：US09881831
申请日：2001-06-14
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L214763
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，形成不希望的空隙的可能性。在互连线路中减少。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

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