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31. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

32. 发明授权

US06448594B1 Method and system for processing a semiconductor device 有权
标题翻译：用于处理半导体器件的方法和系统
公开(公告)号：US06448594B1
公开(公告)日：2002-09-10
申请号：US09539307
申请日：2000-03-30
申请人： Maria C. Chan , Hao Fang , Lu You , Mark S. Chang , King Wai Kelwin Ko
发明人： Maria C. Chan , Hao Fang , Lu You , Mark S. Chang , King Wai Kelwin Ko
IPC分类号： H01L2976
CPC分类号： H01L21/823468 , H01L21/823425 , Y10S257/90
摘要： In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped. In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape. Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.
摘要翻译：在本发明的第一方面中，公开了一种半导体器件。半导体器件包括至少两个栅极堆叠，每个栅极堆叠体具有在所述至少两个栅极堆叠中的每一个的两侧上的两个侧面和氧化物间隔物，其中至少一个氧化物间隔物是三角形的。在本发明的第二方面中，公开了一种用于处理半导体器件的方法和系统。用于处理半导体的方法和系统包括在半导体衬底上形成至少两个栅极叠层，在所述至少两个栅极堆叠上沉积氧化物层，以及蚀刻氧化物层以在至少两个栅极堆叠之间形成至少一个氧化物间隔物栅堆叠，其中所述至少一个氧化物间隔物是三角形的。通过使用本发明，消除了在常规半导体处理期间在半导体器件中产生的空隙。这通过在蚀刻氧化物层以形成氧化物间隔物时形成具有三角形形状的氧化物间隔物来实现。通过产生三角形氧化物间隔物，随后的材料层可沉积在氧化物间隔物上，而不会在半导体器件中产生空隙。因此，作为使用本发明的结果，氧化物间隔物被加强，这增加了半导体器件的可靠性。

33. 发明授权

US06431182B1 Plasma treatment for polymer removal after via etch 有权
标题翻译：通过蚀刻后的聚合物去除的等离子体处理
公开(公告)号：US06431182B1
公开(公告)日：2002-08-13
申请号：US09427861
申请日：1999-10-27
申请人： Mohammad R. Rakhshandehroo , Mark S. Chang , Angela T. Hui
发明人： Mohammad R. Rakhshandehroo , Mark S. Chang , Angela T. Hui
IPC分类号： B08B600
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76814
摘要： A method and article of manufacture of a via in a semiconductor layered device. The method can include applying an OH/H containing plasma, such as H2O or O2 or a forming gas, to a via which has been etched in a layer of the device. A mixture of oxygen and fluorine-based plasma is applied to complete cleaning of the via to provide a clean via with very little loss of dimensional and surface quality. In another aspect the OH/H containing plasma and the oxygen and fluorine-based plasma are applied together to clean the via.
摘要翻译：半导体分层器件中的通孔的制造方法和制造方法。该方法可以包括将OH / H等离子体（例如H 2 O或O 2或形成气体）施加到在器件的层中被蚀刻的通孔。施加氧和氟基等离子体的混合物以完成通孔的清洁以提供清洁的通孔，其尺寸和表面质量几乎没有损失。另一方面，将包含OH / H的等离子体和基于氧和氟的等离子体一起施加以清洁通孔。

34. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

35. 发明授权

US06249036B1 Stepper alignment mark formation with dual field oxide process 失效
标题翻译：步进对准标记形成与双场氧化法
公开(公告)号：US06249036B1
公开(公告)日：2001-06-19
申请号：US09044389
申请日：1998-03-18
申请人： Tatsuya Kajita , Mark S. Chang
发明人： Tatsuya Kajita , Mark S. Chang
IPC分类号： H01L2900
CPC分类号： G03F7/0035 , H01L23/544 , H01L27/1052 , H01L2223/5442 , H01L2223/54453 , H01L2223/5446 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material. The method includes the steps of: (a) providing a first photomask member having mask portions for forming a plurality of first field oxide regions on a first region of a semiconductor substrate and also having a mask portion for forming an alignment marker; (b) providing a second photomask member having mask portions for forming a plurality of second field oxide regions on a second region of the semiconductor substrate and also having mask portions delineated for covering any first field oxide regions and alignment marker formed by using the first photomask member; (c) forming the first field oxide regions and the alignment marker utilizing the first photomask member; (d) covering the formed first field oxide regions and the alignment marker with a photoresist material by utilizing the second photomask member; (e) forming the second field oxide regions after utilizing the second photomask member; (f) facilitating wafer alignment accuracy by removing the photoresist material and exposing the alignment marker; and (g) aligning a semiconductor wafer by utilizing the exposed alignment marker. The mask set can be used in conjunction with stepper wafer alignment tools and is especially useful in forming a memory semiconductor product capable of performing block data erasure operations. The exposed alignment marker facilitates checking and testing mask misalignment during the fabrication process.
摘要翻译：一种用于在半导体制造工艺中产生晶片对准精度的半导体光掩模组。光掩模组产生对准标记，其在进行双场氧化物（FOX）制造工艺之后的后续制造中是准确的。现有技术的方法传统上用氧化物材料层覆盖对准标记。该方法包括以下步骤：（a）提供具有用于在半导体衬底的第一区域上形成多个第一场氧化物区域的掩模部分并且还具有用于形成对准标记的掩模部分的第一光掩模构件; （b）提供具有掩模部分的第二光掩模部件，用于在半导体衬底的第二区域上形成多个第二场氧化物区域，并且还具有描绘用于覆盖任何第一场氧化物区域的掩模部分和使用第一光掩模形成的对准标记会员; （c）利用第一光掩模构件形成第一场氧化物区域和对准标记; （d）利用第二光掩模件覆盖所形成的第一场氧化物区域和对准标记物与光致抗蚀剂材料; （e）在利用第二光掩模构件之后形成第二场氧化物区域; （f）通过去除光致抗蚀剂材料并暴露对准标记物来促进晶片对准精度; 和（g）通过利用曝光的对准标记对准半导体晶片。掩模组可与步进晶片对准工具结合使用，并且特别适用于形成能够执行块数据擦除操作的存储器半导体产品。暴露的对准标记有助于在制造过程中检查和测试掩模未对准。

36. 发明授权

US5679608A Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC 失效
标题翻译：用于实现生产有价值，低电介质，低电介质，低互连电阻和高性能IC的加工技术
公开(公告)号：US5679608A
公开(公告)日：1997-10-21
申请号：US463448
申请日：1995-06-05
申请人： Robin W. Cheung , Mark S. Chang
发明人： Robin W. Cheung , Mark S. Chang
IPC分类号： H01L21/28 , H01L21/027 , H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L23/53242 , H01L23/53228 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , Y10S148/10 , Y10S148/106 , Y10S438/95 , Y10S438/951
摘要： The interconnects in a semiconductor device contacting metal lines includes a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist includes a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
摘要翻译：接触金属线的半导体器件中的互连包括诸如铜，金，银或铂的低电阻金属，并且由具有低介电常数的材料例如苯并环丁烯或其衍生物分离。使用三层抗蚀剂结构以及剥离工艺来形成互连。低介电常数材料为低电阻金属的扩散提供扩散阻挡层。三层抗蚀剂包括可溶解聚合物的第一层，硬掩模材料的第二层和抗蚀剂材料的第三层。所得到的结构提供了具有增加的速度和易于制造的集成电路。

37. 发明授权

US08283718B2 Integrated circuit system with metal and semi-conducting gate 有权
标题翻译：具有金属和半导体栅极的集成电路系统
公开(公告)号：US08283718B2
公开(公告)日：2012-10-09
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

38. 发明授权

US07374654B1 Method of making an organic memory cell 有权
标题翻译：制造有机记忆体的方法
公开(公告)号：US07374654B1
公开(公告)日：2008-05-20
申请号：US10978845
申请日：2004-11-01
申请人： Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian
发明人： Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian
IPC分类号： C25F3/00 , C25F7/00 , C25D5/18 , C25D5/10 , B23H7/00
CPC分类号： C23C28/00 , G11C13/0014 , G11C13/0016 , G11C2213/56 , H01L27/285
摘要： A method of making an organic memory cell which comprises two electrodes with a controllably conductive media between the two electrodes is disclosed. The present invention involves providing a dielectric layer having formed therein one or more first electrode pads; removing a portion of the first electrode pad to form a recessed area on top of the pads and in the dielectric layer using reverse electroplating; forming a controllably conductive media over the first electrode pad in the recessed area; and forming a second electrode over the conductive media. The controllably conductive media contains an organic semiconductor layer and a passive layer.
摘要翻译：公开了一种制造有机存储单元的方法，该方法包括在两个电极之间具有可控导电介质的两个电极。本发明涉及提供在其中形成有一个或多个第一电极焊盘的电介质层; 去除所述第一电极焊盘的一部分以在所述焊盘的顶部和所述电介质层中使用反向电镀形成凹陷区域; 在所述凹陷区域中的所述第一电极焊盘上形成可控导电介质; 以及在所述导电介质上形成第二电极。可控导电介质包含有机半导体层和无源层。

39. 发明授权

US06979619B1 Flash memory device and a method of fabrication thereof 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US06979619B1
公开(公告)日：2005-12-27
申请号：US09941370
申请日：2001-08-28
申请人： Hao Fang , Yue-Song He , Mark S. Chang , Kent K. Chang
发明人： Hao Fang , Yue-Song He , Mark S. Chang , Kent K. Chang
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11543
摘要： In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer. According to the present invention, the method for fabricating the flash memory device is a simplified process that results in a significant improvement in the oxide reliability in the core and periphery areas and also eliminates the nitrogen contamination problem in the periphery area.
摘要翻译：在本发明的第一方面中，公开了一种制造闪速存储器件的方法。该方法包括以下步骤：在存储器件的外围区域中提供双栅极氧化物的一部分，然后在存储器件的核心区域中同时提供双栅极氧化物，并在周边区域中完成双栅极氧化物。最后，在上述步骤之后，在核心区域和外围区域都提供氮化处理。在本发明的第二方面，公开了一种闪速存储器件。闪存器件包括具有包括氧化物层，第一多晶硅层，多晶硅间介电层和第二多晶硅层的多个存储晶体管的核心区域。闪存器件还包括具有包括氧化物层，第一多晶硅层的一部分和第二多晶硅层的多个晶体管的外围区域。根据本发明，用于制造闪速存储器件的方法是简化的工艺，其显着提高了芯部和外围区域中的氧化物可靠性，并且还消除了周边区域中的氮污染问题。

40. 发明授权

US06900488B1 Multi-cell organic memory element and methods of operating and fabricating 有权
标题翻译：多单元有机存储元件及其操作和制造方法
公开(公告)号：US06900488B1
公开(公告)日：2005-05-31
申请号：US10284946
申请日：2002-10-31
申请人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
发明人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
IPC分类号： H01L27/28 , H01L51/00 , H01L51/30 , H01L51/40 , H01L29/76
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0021 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e.g., read/write) between the top electrodes and bottom electrode, respectively. In this manner, multiple storage cells can be formed within a singular organic structure thereby increasing memory device density and storage.
摘要翻译：本发明提供一种多小区有机存储装置，其可以作为具有构造在存储装置内的多个多小区结构的非易失性存储装置来操作。可以形成下电极，其中在下电极的顶部上形成一个或多个钝化层。在无源层和下电极之上形成层间电介质（ILD），由此在ILD内产生通孔或其它类型的浮雕，然后利用有机半导体材料部分地填充钝化层以上的通孔。通孔中没有填充有机材料的部分用电介质材料填充，从而在钝化层或下层电极之上形成多维存储结构。然后在存储器结构上方添加一个或多个顶部电极，由此在存储器结构的有机部分内分别创建独特的存储单元，并分别在顶部电极和底部电极之间激活（例如，读取/写入）。以这种方式，可以在单个有机结构内形成多个存储单元，从而增加存储器件密度和存储。

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