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31. 发明授权

US08502283B2 Strained fully depleted silicon on insulator semiconductor device 有权
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件
公开(公告)号：US08502283B2
公开(公告)日：2013-08-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

32. 发明授权

US08482963B1 Integrated circuits with asymmetric and stacked transistors 有权
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US08482963B1
公开(公告)日：2013-07-09
申请号：US12629831
申请日：2009-12-02
申请人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

33. 发明授权

US07923785B2 Field effect transistor having increased carrier mobility 有权
标题翻译：场效应晶体管的载流子迁移率增加
公开(公告)号：US07923785B2
公开(公告)日：2011-04-12
申请号：US10643461
申请日：2003-08-18
申请人： Qi Xiang , Boon-Yong Ang , Jung-Suk Goo
发明人： Qi Xiang , Boon-Yong Ang , Jung-Suk Goo
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/02 , H01L29/4925 , H01L29/513 , H01L29/78 , H01L29/7845 , Y10S438/938
摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.
摘要翻译：根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致增加FET中的载流子迁移率。例如，第二热膨胀系数可以大于第一热膨胀系数。载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

34. 发明申请

US20090047770A1 METHOD OF FORMING ISOLATION REGIONS FOR INTEGRATED CIRCUITS 有权
标题翻译：形成集成电路隔离区的方法
公开(公告)号：US20090047770A1
公开(公告)日：2009-02-19
申请号：US12205361
申请日：2008-09-05
申请人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
发明人： Haihong Wang , Minh-Van Ngo , Qi Xiang , Paul R. Besser , Eric N. Paton , Ming-Ren Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L29/1054
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。低温过程可以是ALD过程。

35. 发明授权

US07306997B2 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor 失效
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件及其制造方法
公开(公告)号：US07306997B2
公开(公告)日：2007-12-11
申请号：US10986399
申请日：2004-11-10
申请人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold P. Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

36. 发明授权

US07138302B2 Method of fabricating an integrated circuit channel region 有权
标题翻译：制造集成电路通道区域的方法
公开(公告)号：US07138302B2
公开(公告)日：2006-11-21
申请号：US10755763
申请日：2004-01-12
申请人： Qi Xiang , James N. Pan , Jung-Suk Goo
发明人： Qi Xiang , James N. Pan , Jung-Suk Goo
IPC分类号： H01L21/335 , H01L21/84 , H01L21/338 , H01L21/8249 , H01L27/01
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842
摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.
摘要翻译：示例性实施例涉及FinFET沟道结构形成的方法。该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。

37. 发明授权

US07091097B1 End-of-range defect minimization in semiconductor device 有权
标题翻译：半导体器件的范围内缺陷最小化
公开(公告)号：US07091097B1
公开(公告)日：2006-08-15
申请号：US10933424
申请日：2004-09-03
申请人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
发明人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

38. 发明授权

US07078299B2 Formation of finFET using a sidewall epitaxial layer 有权
标题翻译：使用侧壁外延层形成finFET
公开(公告)号：US07078299B2
公开(公告)日：2006-07-18
申请号：US10654631
申请日：2003-09-03
申请人： Witold P. Maszara , Jung-Suk Goo , James N. Pan , Qi Xiang
发明人： Witold P. Maszara , Jung-Suk Goo , James N. Pan , Qi Xiang
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , A61F5/3776 , H01L29/1054 , H01L29/66795 , H01L29/78687 , Y10S438/933
摘要： A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.
摘要翻译：使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

39. 发明申请

US20050153486A1 Method of fabricating a strained silicon channel FinFET 有权
标题翻译：制造应变硅沟道FinFET的方法
公开(公告)号：US20050153486A1
公开(公告)日：2005-07-14
申请号：US10755763
申请日：2004-01-12
申请人： Qi Xiang , James Pan , Jung-Suk Goo
发明人： Qi Xiang , James Pan , Jung-Suk Goo
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00 , H01L21/8234
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842
摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.
摘要翻译：示例性实施例涉及FinFET沟道结构形成的方法。该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。

40. 发明申请

US20050151222A1 Shallow trench isolation process and structure with minimized strained silicon consumption 有权
标题翻译：浅沟槽隔离工艺和结构，使应变硅消耗最小化
公开(公告)号：US20050151222A1
公开(公告)日：2005-07-14
申请号：US10755602
申请日：2004-01-12
申请人： Qi Xiang , James Pan , Jung-Suk Goo
发明人： Qi Xiang , James Pan , Jung-Suk Goo
IPC分类号： H01L21/336 , H01L21/762 , H01L29/10 , H01L29/45 , H01L29/786 , H01L21/76 , H01L29/00
CPC分类号： H01L29/66742 , H01L21/76283 , H01L29/458 , H01L29/7842 , H01L29/78687 , Y10S438/933
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。在形成沟槽之后形成应变材料。该方法可以用在盒层上方的化合物半导体层上。

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