专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050153486A1 Method of fabricating a strained silicon channel FinFET 有权
标题翻译：制造应变硅沟道FinFET的方法
公开(公告)号：US20050153486A1
公开(公告)日：2005-07-14
申请号：US10755763
申请日：2004-01-12
申请人： Qi Xiang , James Pan , Jung-Suk Goo
发明人： Qi Xiang , James Pan , Jung-Suk Goo
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00 , H01L21/8234
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7842
摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.
摘要翻译：示例性实施例涉及FinFET沟道结构形成的方法。该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。

2. 发明申请

US20050151222A1 Shallow trench isolation process and structure with minimized strained silicon consumption 有权
标题翻译：浅沟槽隔离工艺和结构，使应变硅消耗最小化
公开(公告)号：US20050151222A1
公开(公告)日：2005-07-14
申请号：US10755602
申请日：2004-01-12
申请人： Qi Xiang , James Pan , Jung-Suk Goo
发明人： Qi Xiang , James Pan , Jung-Suk Goo
IPC分类号： H01L21/336 , H01L21/762 , H01L29/10 , H01L29/45 , H01L29/786 , H01L21/76 , H01L29/00
CPC分类号： H01L29/66742 , H01L21/76283 , H01L29/458 , H01L29/7842 , H01L29/78687 , Y10S438/933
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。在形成沟槽之后形成应变材料。该方法可以用在盒层上方的化合物半导体层上。

3. 发明授权

US07012007B1 Strained silicon MOSFET having improved thermal conductivity and method for its fabrication 失效
标题翻译：具有改进的导热性的应变硅MOSFET及其制造方法
公开(公告)号：US07012007B1
公开(公告)日：2006-03-14
申请号：US10658479
申请日：2003-09-09
申请人： Jung-Suk Goo , Qi Xiang , James Pan
发明人： Jung-Suk Goo , Qi Xiang , James Pan
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/1054 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： A strained silicon MOSFET employs a high thermal conductivity insulating material in the trench isolations to dissipate thermal energy generated in the MOSFET and to avoid self-heating caused by the poor thermal conductivity of an underlying silicon germanium layer. The high thermal conductivity material is preferably silicon carbide, and the isolations preferably extend through the silicon germanium layer to contact an underlying silicon layer so as to conduct thermal energy from the active region to the silicon layer.
摘要翻译：应变硅MOSFET在沟槽隔离中采用高导热绝缘材料，以消散MOSFET中产生的热能，并避免由于下层硅锗层导热性差导致的自发热。高导热性材料优选为碳化硅，并且隔离优选延伸穿过硅锗层以接触下面的硅层，以便将热能从有源区传导到硅层。

4. 发明申请

US20050048727A1 FORMATION OF FINFET USING A SIDEWALL EPITAXIAL LAYER 有权
标题翻译：使用边墙外延层形成FINFET
公开(公告)号：US20050048727A1
公开(公告)日：2005-03-03
申请号：US10654631
申请日：2003-09-03
申请人： Witold Maszara , Jung-Suk Goo , James Pan , Qi Xiang
发明人： Witold Maszara , Jung-Suk Goo , James Pan , Qi Xiang
IPC分类号： A61F5/37 , H01L21/336 , H01L29/10 , H01L29/786
CPC分类号： H01L29/785 , A61F5/3776 , H01L29/1054 , H01L29/66795 , H01L29/78687 , Y10S438/933
摘要： A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.
摘要翻译：使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

5. 发明授权

US07015078B1 Silicon on insulator substrate having improved thermal conductivity and method of its formation 有权
标题翻译：绝缘体上硅衬底具有改进的导热性及其形成方法
公开(公告)号：US07015078B1
公开(公告)日：2006-03-21
申请号：US10658668
申请日：2003-09-09
申请人： Qi Xiang , Jung-Suk Goo , James Pan
发明人： Qi Xiang , Jung-Suk Goo , James Pan
IPC分类号： H01L21/00
CPC分类号： H01L29/78603 , H01L21/76254 , H01L29/66795 , H01L29/785 , H01L29/78687
摘要： A silicon on insulator (SOI) substrate includes a layer of silicon carbide beneath an insulating layer on which semiconductor devices are formed. The silicon carbide layer has a high thermal conductivity and provides beneficial dissipation of thermal energy generated by the devices. The SOI substrate may be formed by a bonding method. SOI MOSFET devices using the SOI substrate are also disclosed.
摘要翻译：绝缘体上硅（SOI）衬底包括在其上形成有半导体器件的绝缘层下方的碳化硅层。碳化硅层具有高导热性，并提供由器件产生的热能的有益耗散。 SOI衬底可以通过接合方法形成。还公开了使用SOI衬底的SOI MOSFET器件。

6. 发明申请

US20050048743A1 Method of growing as a channel region to reduce source/drain junction capicitance 有权
标题翻译：作为渠道区域生长以减少源/汇交汇率资本的方法
公开(公告)号：US20050048743A1
公开(公告)日：2005-03-03
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
发明人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

7. 发明授权

US08772169B2 Technique for controlling trench profile in semiconductor structures 有权
公开(公告)号：US08772169B2
公开(公告)日：2014-07-08
申请号：US12109302
申请日：2008-04-24
申请人： Hui Chen , Qi Wang , Briant Harward , James Pan
发明人： Hui Chen , Qi Wang , Briant Harward , James Pan
IPC分类号： H01L21/311
摘要： A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

8. 发明授权

US08669623B2 Structure related to a thick bottom dielectric (TBD) for trench-gate devices 有权
标题翻译：与沟槽栅极器件的厚底部电介质（TBD）有关的结构
公开(公告)号：US08669623B2
公开(公告)日：2014-03-11
申请号：US12870600
申请日：2010-08-27
申请人： James Pan , Christopher Lawrence Rexer
发明人： James Pan , Christopher Lawrence Rexer
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/8725
摘要： A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.
摘要翻译：包括屏蔽栅极的半导体结构如下形成。使用掩模在半导体区域中形成多个沟槽。掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。形成在每个沟槽的至少下侧壁延伸的屏蔽电介质。沿每个沟槽的底部形成厚底部电介质（TBD）。第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。屏蔽电极形成在每个沟槽的底部。在每个沟槽中的屏蔽电极之上形成栅电极。

9. 发明授权

US08541840B2 Structure and method for semiconductor power devices 有权
标题翻译：半导体功率器件的结构和方法
公开(公告)号：US08541840B2
公开(公告)日：2013-09-24
申请号：US13028054
申请日：2011-02-15
申请人： James Pan
发明人： James Pan
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/0635 , H01L29/1087 , H01L29/4175 , H01L29/78624
摘要： A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.
摘要翻译：半导体器件包括在衬底上的绝缘体上半导体区域。绝缘体上半导体区域包括覆盖电介质区域的第一半导体区域。该器件包括MOS晶体管和双极晶体管。 MOS晶体管在第一半导体区域中具有漏极区域，体区域和源极区域。 MOS晶体管还包括一个栅极。该器件还包括覆盖衬底并且与漏极区相邻的第二半导体区域，以及覆盖衬底并与第二半导体区域相邻的第三半导体区域。双极晶体管包括MOS晶体管的漏极区域作为发射极，第二半导体区域作为基极，第三半导体区域作为集电极。因此，MOS晶体管的漏极也用作双极晶体管的发射极。此外，栅极和基极通过电阻元件耦合。

10. 发明授权

US08329538B2 Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein 有权
标题翻译：屏蔽栅沟槽FET，其中具有低k电介质的电极间电介质
公开(公告)号：US08329538B2
公开(公告)日：2012-12-11
申请号：US13083253
申请日：2011-04-08
申请人： James Pan , James J. Murphy
发明人： James Pan , James J. Murphy
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66727 , H01L29/66734
摘要： A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
摘要翻译：一种用于形成屏蔽栅极沟道场效应晶体管（FET）的方法包括在半导体区域中形成沟槽，在每个沟槽的底部形成屏蔽电极，并形成在屏蔽电极上延伸的电极间电介质（IED）。 IED可以包括低k电介质。该方法还包括在IED上的每个沟槽的上部形成栅电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式