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31. 发明授权

US5899732A Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device 失效
标题翻译：通过多晶硅栅极注入硅的方法，用于半导体器件的穿通控制
公开(公告)号：US5899732A
公开(公告)日：1999-05-04
申请号：US837937
申请日：1997-04-11
申请人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
发明人： Mark I. Gardner , Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore
IPC分类号： H01L21/225 , H01L21/265 , H01L21/322 , H01L21/336 , H01L21/8238 , H01L29/10
CPC分类号： H01L29/66492 , H01L21/2253 , H01L21/26506 , H01L21/26513 , H01L21/3221 , H01L21/8238 , H01L29/1083 , H01L29/6659
摘要： A region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate. The region of damaged silicon is formed between source and drain regions of a device by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device. The damaged region is subsequently annealed and, during the annealing process, dopant atoms such as boron segregate to the region, locally increasing the dopant concentration in the region. The previously damaged region is in a location that determine the punchthrough characteristics of the device. The silicon implant for creating a gettering effect is performed after gate formation so that the region immediately beneath the junction is maintained at a lower dopant concentration to reduce junction capacitance. Silicon is implanted in the vicinity of a polysilicon gate to induce transient-enhanced diffusion (TED) of dopant atoms such as boron or phosphorus for control of punchthrough characteristics of a device. A punchthrough control implant is performed following formation of gate electrodes on a substrate using a self-aligned gettering implant.
摘要翻译：受损硅的区域被用作吸杂硅衬底中的杂质的吸杂区域。损坏的硅的区域在器件的栅极电极形成之后通过将硅原子注入到硅衬底中而在器件的源极和漏极区域之间形成。受损区域随后退火，并且在退火过程期间，诸如硼的掺杂剂原子偏析到该区域，局部地增加该区域中的掺杂剂浓度。先前损坏的区域位于确定设备穿透特性的位置。用于产生吸杂效应的硅植入物在栅极形成之后进行，使得紧邻在结点处的区域保持在较低掺杂剂浓度以减小结电容。将硅注入到多晶硅栅极附近以引发诸如硼或磷的掺杂剂原子的瞬态增强扩散（TED），以控制器件的穿透特性。在使用自对准吸气植入物在衬底上形成栅电极之后执行穿通控制植入。

32. 发明授权

US5888675A Reticle that compensates for radiation-induced lens error in a photolithographic system 失效
标题翻译：补偿光刻系统中辐射诱发的透镜误差的光罩
公开(公告)号：US5888675A
公开(公告)日：1999-03-30
申请号：US760031
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F1/00 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F7/70433 , G03F1/70 , G03F7/70241
摘要： A reticle provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions, for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.
摘要翻译：掩模版提供图像图案并补偿光刻系统中的透镜误差。使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。可以通过调节辐射透射区域的构造（或布局）来结构地修改掩模版，例如通过调节石英基底的顶表面上的铬图案。或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

33. 发明授权

US5885877A Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
标题翻译：复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译：复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层，并通过原位沉积氮掺杂的第一多晶硅层。完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

34. 发明授权

US06661057B1 Tri-level segmented control transistor and fabrication method 失效
标题翻译：三电平分段控制晶体管及其制造方法
公开(公告)号：US06661057B1
公开(公告)日：2003-12-09
申请号：US09056836
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L27088
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/32053 , H01L21/76802 , H01L21/76855 , H01L29/66484 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7833 , Y10S257/90
摘要： A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.
摘要翻译：晶体管形成在具有分段栅极结构的有源区中。分段栅结构有利地提供了在晶体管内形成的沟道区的动态控制。轻掺杂的源极和漏极（LDD）区域形成为与栅电极对准。在与栅电极的暴露表面相邻形成绝缘层之后，形成布置在LDD区域上方的导电间隔物。这些间隔物通过绝缘层与栅电极电隔离。形成重掺杂的源极和漏极（S / D）区域，其与间隔物对准，并且例如通过提供给导电间隔物，栅电极和S / D区域的自对准硅化物工艺进行电接触。所描述的结构有利地通过对S / D区域的LDD部分的动态独立控制来提供通道区域的动态控制。

35. 发明授权

US06410409B1 Implanted barrier layer for retarding upward diffusion of substrate dopant 失效
标题翻译：用于延缓衬底掺杂剂的向上扩散的植入阻挡层
公开(公告)号：US06410409B1
公开(公告)日：2002-06-25
申请号：US08741799
申请日：1996-10-31
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21265
CPC分类号： H01L21/8238 , H01L21/26506 , H01L21/26513 , H01L21/74
摘要： Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P− substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.
摘要翻译：在随后的热处理操作（例如退火）期间，在半导体衬底内形成深P +层的硼向上扩散。用于延迟硼的这种向上扩散的方法包括注入氮以在P +层的上边界附近形成氮阻挡层，并且远低于晶体管源/漏区。一个实施例包括形成在下面的P +衬底上的轻掺杂的外延层。在另一个实施例中，深硼注入在P-衬底内形成P +层，并提供外延层的许多优点，而不需要这样的外延层。以1-3MeV的优选能量进行氮注入，以在1-5微米范围内的深度形成注入的氮阻挡层。氧也可以被植入以形成扩散阻挡层，以阻止形成深N +层的砷或磷的向上扩散。

36. 发明授权

US06403445B1 Enhanced trench isolation structure 失效
标题翻译：增强沟槽隔离结构
公开(公告)号：US06403445B1
公开(公告)日：2002-06-11
申请号：US09286729
申请日：1999-04-06
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21762
CPC分类号： H01L21/76888 , H01L21/76224 , H01L21/76834 , H01L21/76895 , H01L21/823878
摘要： An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.
摘要翻译：对于一个实施例，沟槽隔离形成的改进方法包括在平坦化沟槽之上施加多晶硅层，并且在刻蚀有源区之前将多晶硅转化为氧化物。这种转化的氧化物比通常用于填充沟槽（例如TEOS）的材料更致密，并且导致较少的沟槽隔离区的过蚀刻。因此，电介质隔离的质量得到改善，特别是较小的漏电流流过沟槽隔离区。此外，较少的漏电流从随后形成的局部互连层流出。

37. 发明授权

US06380055B2 Dopant diffusion-retarding barrier region formed within polysilicon gate layer 有权
标题翻译：在多晶硅栅极层内形成的掺杂扩散阻滞层
公开(公告)号：US06380055B2
公开(公告)日：2002-04-30
申请号：US09177043
申请日：1998-10-22
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L213205
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/32155
摘要： A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 Å thick. Any nitrogen residing at the top of the gate dielectric may be kept to a concentration less than approximately 2%. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness of approximately 25-60 Å, when using a p-type dopant, such as boron.
摘要翻译：扩散阻滞屏障区域被结合到栅电极中以减少掺杂剂朝向栅极电介质的向下扩散。阻挡区域是在两个单独形成的多晶硅层之间形成的含氮扩散阻滞区域。多晶硅的上层比多晶硅的下层掺杂更多，并且势垒区域用于将大部分掺杂剂保持在多晶硅的上层内，并且还可以允许一些掺杂剂扩散到多晶硅的下层。阻挡区域可以例如通过在含氮环境中退火第一多晶硅层以在第一多晶硅层的顶表面处形成氮化层而形成。可以通过在第一多晶硅层的顶表面上沉积含氮层，例如氮化硅或氮化钛层来形成阻挡区。含氮层的厚度优选为约5〜约厚。驻留在栅极电介质顶部的任何氮可以保持在小于约2％的浓度。当使用诸如硼的p型掺杂剂时，本发明特别适用于薄栅极电介质，例如厚度大约为25埃的那些。

38. 发明授权

US06268637B1 Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication 有权
标题翻译：通过制造用于低K隔离高级CMOS制造的横向EPI桥来制造气隙隔离的方法
公开(公告)号：US06268637B1
公开(公告)日：2001-07-31
申请号：US09178080
申请日：1998-10-22
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L2900
CPC分类号： H01L21/823878 , H01L21/764
摘要： An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulating sidewall. A bridge layer is formed between the first and the second sidewalls. The bridge layer, the first and second sidewalls, and the substrate define an air gap in the trench. The isolation structure exhibits a low capacitance in a narrow structure. Scaling is enhanced and the potential for parasitic leakage current due to non-planarity is reduced.
摘要翻译：提供隔离结构及其制造方法。在一个方面，该方法包括以下步骤：在衬底中形成沟槽并在沟槽中形成第一绝缘侧壁，并在沟槽中形成与第一绝缘侧壁间隔开的第二绝缘体。桥接层形成在第一和第二侧壁之间。桥接层，第一和第二侧壁以及衬底在沟槽中限定气隙。隔离结构在窄结构中表现出低电容。缩放增强，并且由于非平面性引起的寄生漏电流的可能性降低。

39. 发明授权

US06225151B1 Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion 失效
标题翻译：晶体管源极/漏极区域之下的氮衬垫以延迟掺杂剂扩散
公开(公告)号：US06225151B1
公开(公告)日：2001-05-01
申请号：US08871469
申请日：1997-06-09
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L2122
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28176 , H01L21/28202 , H01L21/823814 , H01L29/1033 , H01L29/518 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7833
摘要： A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source. Such a liner is particularly advantageous for boron-doped source/drain regions, and may be combined with N-channel IGFETs formed without such liners.
摘要翻译：基本上在IGFET的源极/漏极区域下方大致相邻地形成的氮注入区域形成衬垫，以在随后的热处理操作（例如退火步骤）期间阻止源极/漏极掺杂剂原子的扩散。可以在将源极/漏极掺杂剂注入较低深度之前通过将氮注入给定深度来形成氮衬垫。也可以将氮气引入到栅电极下面的IGFET沟道区域的区域中，以阻止源极/漏极掺杂剂的随后的横向扩散。可以使用一个或多个成角度的注入步骤来实现这种氮引入，或者可以通过使用与栅电极对准的垂直注入形成的注入氮层退火来实现。衬垫可以形成在IGFET的漏极侧或源极和漏极两侧，并且可以形成在漏极和/或源极的重掺杂区域的轻掺杂区域下方。这种衬垫对于硼掺杂的源极/漏极区域是特别有利的，并且可以与没有这样的衬垫形成的N沟道IGFET组合。

40. 发明授权

US06197645B1 Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls 失效
标题翻译：制造具有较高的源极/漏极区域的IGFET的方法，其紧邻具有倾斜侧壁的栅极
公开(公告)号：US06197645B1
公开(公告)日：2001-03-06
申请号：US08837539
申请日：1997-04-21
申请人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
发明人： Mark W. Michael , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/41775 , H01L29/41783 , H01L29/42376
摘要： An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, and depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region. The elevated source and drain regions are separated from the lower gate level due to a retrograde slope of the sidewalls of the lower gate level, and the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the semiconducting layer. The method also includes implanting a dopant into the elevated source and drain regions, and diffusing the dopant from the elevated source and drain regions into the underlying source and drain regions. Preferably, the semiconducting layer is deposited by epitaxial deposition, the lower gate level is substantially thicker than the semiconducting layer, the elevated source and drain regions include sidewalls beneath and substantially aligned with sidewalls of the upper gate level, and all source/drain doping in the underlying source and drain regions is diffused from the elevated source and drain regions. In this manner, a highly miniaturized IGFET can be provided with shallow channel junctions without the need for sidewall spacers adjacent to the gate.
摘要翻译：公开了一种IGFET，其具有与具有倾斜侧壁的栅极紧密相邻的源极和漏极区域。制造IGFET的方法包括在半导体衬底上形成较低的栅极电平，其中下部栅极级别包括顶部表面，底部表面和倾斜的相对侧壁，并且顶部表面具有比底部表面大得多的长度，以及在半导体衬底的下栅极电平和下面的源极和漏极区域上沉积半导体层以在下部栅极电平上形成上部栅极电平，在下部源极区域上形成升高的源极区域，以及在下部栅极漏区。由于下栅极电平的侧壁的逆向斜率，升高的源极和漏极区域与下部栅极电平分离，并且由于在栅极栅极电平上缺乏阶跃覆盖，升高的源极和漏极区域与上部栅极电平分离半导体层。该方法还包括将掺杂剂注入到升高的源极和漏极区域中，并且将掺杂剂从升高的源极和漏极区域扩散到下面的源极和漏极区域中。优选地，半导体层通过外延沉积沉积，下栅极电平基本上比半导电层更厚，升高的源极和漏极区域包括在上部栅极电平的侧壁下面并基本对齐的侧壁，并且所有源极/漏极掺杂底层源极和漏极区域从升高的源极和漏极区域扩散。以这种方式，高度小型化的IGFET可以设置有浅沟道结，而不需要邻近门的侧壁间隔。

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