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    • 34. 发明授权
    • Manufacturing seedless barrier layers in integrated circuits
    • 在集成电路中制造无核屏障层
    • US06893955B1
    • 2005-05-17
    • US10328347
    • 2002-12-24
    • Sergey D. LopatinPin-Chin Connie Wang
    • Sergey D. LopatinPin-Chin Connie Wang
    • H01L23/532H01L21/4763
    • H01L23/53238H01L23/53223H01L23/5329H01L2924/0002H01L2924/00
    • An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.
    • 提供了具有半导体器件的半导体衬底的集成电路制造方法。 在半导体衬底上形成器件电介质层,器件电介质层上的沟道电介质层上形成有开口。 阻挡层对通道开口进行排列,并且导体芯填充阻挡层上的开口。 无核屏障层对开口进行排列,并且导体芯填充无核阻挡层上的开口。 阻挡层沉积在开口中并且包含键合到电介质层的阻挡材料的原子层,结合到阻挡材料层和导体芯的中间材料以及与中间材料结合的导体芯材料。 导体芯与导体芯材料结合。
    • 38. 发明授权
    • Integrated circuit interconnect shunt layer
    • 集成电路互连分流层
    • US06455938B1
    • 2002-09-24
    • US09905479
    • 2001-07-13
    • Pin-Chin Connie WangAmit P. MaratheChristy Mei-Chu Woo
    • Pin-Chin Connie WangAmit P. MaratheChristy Mei-Chu Woo
    • H01L2945
    • H01L23/5226H01L2924/0002H01L2924/00
    • An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.
    • 提供了一种用于具有半导体器件的半导体衬底格栅电路上的集成电路的集成电路及其制造方法。 电介质层位于半导体衬底上,其中设有开口。 阻挡层对开口进行排列,并且第一导体芯填充阻挡层上的开口。 第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。 并联层位于导体芯上方的通孔中。 阻挡层将第二通道和通过开口穿过并联层和第二介电层。 导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。