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1. 发明授权

US07696092B2 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect 有权
标题翻译：使用三元铜合金获得低电阻和大晶粒尺寸互连的方法
公开(公告)号：US07696092B2
公开(公告)日：2010-04-13
申请号：US09994395
申请日：2001-11-26
申请人： Sergey D. Lopatin , Paul R. Besser , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Pin-Chin Connie Wang
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/2885 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.
摘要翻译：一种制造集成电路的方法包括沿着横向侧壁和通孔孔的底部形成阻挡层，并且在通孔中通过材料提供三元铜合金以形成通孔。通孔被配置成通过材料接收三元铜合金并电连接第一导电层和第二导电层。三元铜合金通孔材料有助于通孔具有较低的电阻和增加的晶粒尺寸与人工晶界。

2. 发明授权

US06589408B1 Non-planar copper alloy target for plasma vapor deposition systems 有权
标题翻译：用于等离子体气相沉积系统的非平面铜合金靶
公开(公告)号：US06589408B1
公开(公告)日：2003-07-08
申请号：US10107778
申请日：2002-03-27
申请人： Pin-Chin Connie Wang , Paul R. Besser , Sergey D. Lopatin , Minh Q. Tran
发明人： Pin-Chin Connie Wang , Paul R. Besser , Sergey D. Lopatin , Minh Q. Tran
IPC分类号： C23C1435
CPC分类号： C23C14/3414 , C23C14/3407
摘要： A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.
摘要翻译：非平面靶可以被配置用于等离子体气相沉积（PVD）工艺，其中离子轰击非平面靶，并使存在于非平面靶中的合金原子被敲击松动并形成合金膜层。目标包括具有第一合金浓度的顶部平面部分和具有第二合金浓度的侧部环形部分。侧面环形部分具有端部连接到顶部平面部分的端部。第一合金浓度和第二合金浓度不同。

3. 发明授权

US06861349B1 Method of forming an adhesion layer with an element reactive with a barrier layer 失效
标题翻译：用与阻挡层反应的元件形成粘合层的方法
公开(公告)号：US06861349B1
公开(公告)日：2005-03-01
申请号：US10145944
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76859 , H01L21/76873 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元素进入阻挡材料层上的界面层，在界面层上沉积合金层。植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

4. 发明授权

US06534865B1 Method of enhanced fill of vias and trenches 有权
标题翻译：增强通孔和沟槽填充的方法
公开(公告)号：US06534865B1
公开(公告)日：2003-03-18
申请号：US09880219
申请日：2001-06-12
申请人： Sergey D. Lopatin , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Pin-Chin Connie Wang
IPC分类号： H01L21321
CPC分类号： H01L23/5226 , C23C18/1605 , C25D5/02 , H01L21/3212 , H01L21/76843 , H01L21/76847 , H01L21/76859 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method and apparatus for filling vias and trenches in integrated circuits is provided having a substrate with a device provided thereon. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening provided therein. A barrier layer lines the opening of the channel dielectric. A seed layer is deposited over the barrier layer. Portions of the seed layer are then doped with a material that inhibits the deposition of copper by electroplating or electroless deposition using ion implantation. A conductor core layer is deposited on the seed layer by electroplating or electroless deposition, filling the opening over the barrier layer. The inhibiting material on the doped seed layer creates a filling profile that allows for a more efficient, faster, void-free filling of the conductor core layer.
摘要翻译：提供一种用于在集成电路中填充过孔和沟槽的制造方法和装置，其具有设置在其上的装置的基板。在半导体衬底上形成器件电介质层。器件电介质层上的沟道电介质层具有设置在其中的开口。阻挡层对通道电介质的开口进行排列。种子层沉积在阻挡层上。然后通过使用离子注入的电镀或无电沉积来抑制铜的沉积的材料掺杂种子层的部分。通过电镀或无电沉积将导体芯层沉积在种子层上，填充阻挡层上的开口。掺杂种子层上的抑制材料产生填充轮廓，其允许导体芯层更有效，更快速，无空隙的填充。

5. 发明授权

US07169706B2 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition 失效
标题翻译：使用化学气相沉积（CVD）铜沉积的粘附前体层的方法
公开(公告)号：US07169706B2
公开(公告)日：2007-01-30
申请号：US10687186
申请日：2003-10-16
申请人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Alline F. Myers , Jeremias D. Romero , Minh Q. Tran , Lu You , Pin-Chin Connie Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/76877
摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.
摘要翻译：示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。粘附前体层由气体形成，电介质材料包括孔。

6. 发明授权

US06992004B1 Implanted barrier layer to improve line reliability and method of forming same 有权
标题翻译：植入障碍层提高线路可靠性及其形成方法
公开(公告)号：US06992004B1
公开(公告)日：2006-01-31
申请号：US10209060
申请日：2002-07-31
申请人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
发明人： Paul R. Besser , Matthew S. Buynoski , Minh Q. Tran , Pin-Chin Connie Wang , Lu You , Sergey D. Lopatin , Jeremias D. Romero
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76859 , H01L21/76867
摘要： A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.
摘要翻译：用于制造具有改善的电迁移特性的集成电路的方法包括在层间电介质层中形成孔，并在孔中提供阻挡层。孔被金属材料填充，并且在金属材料上方设有阻挡层。可以在金属材料和阻挡层的界面处形成金属间化合物区域。金属间化合物可以通过种植物形成。

7. 发明授权

US06555909B1 Seedless barrier layers in integrated circuits and a method of manufacture therefor 有权
标题翻译：集成电路中的无核屏障层及其制造方法
公开(公告)号：US06555909B1
公开(公告)日：2003-04-29
申请号：US09760422
申请日：2001-01-11
申请人： Sergey D. Lopatin , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Pin-Chin Connie Wang
IPC分类号： H01L2352
CPC分类号： H01L23/53238 , H01L23/53223 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层，器件电介质层上的沟道电介质层上形成有开口。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。无核屏障层对开口进行排列，并且导体芯填充无核阻挡层上的开口。阻挡层沉积在开口中并且包含键合到电介质层的阻挡材料的原子层，结合到阻挡材料层和导体芯的中间材料以及与中间材料结合的导体芯材料。导体芯与导体芯材料结合。

8. 发明授权

US06815340B1 Method of forming an electroless nucleation layer on a via bottom 有权
标题翻译：在通孔底部形成无电解成核层的方法
公开(公告)号：US06815340B1
公开(公告)日：2004-11-09
申请号：US10145928
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76846 , H01L21/76849 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.
摘要翻译：制造集成电路的方法可以包括执行反应离子蚀刻（RIE）以在电介质层中形成通孔，其中通孔孔暴露位于电介质层下面的导电层的一部分，从RIE除去聚合物残余物，以及使用合金在导电层的暴露部分上形成成核层。成核层可以在无电解过程中形成，并且可以提高电迁移可靠性，降低通孔电阻，消除通孔腐蚀，并消除电介质侧壁上的铜再溅射。

9. 发明授权

US06893955B1 Manufacturing seedless barrier layers in integrated circuits 有权
标题翻译：在集成电路中制造无核屏障层
公开(公告)号：US06893955B1
公开(公告)日：2005-05-17
申请号：US10328347
申请日：2002-12-24
申请人： Sergey D. Lopatin , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Pin-Chin Connie Wang
IPC分类号： H01L23/532 , H01L21/4763
CPC分类号： H01L23/53238 , H01L23/53223 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路制造方法。在半导体衬底上形成器件电介质层，器件电介质层上的沟道电介质层上形成有开口。阻挡层对通道开口进行排列，并且导体芯填充阻挡层上的开口。无核屏障层对开口进行排列，并且导体芯填充无核阻挡层上的开口。阻挡层沉积在开口中并且包含键合到电介质层的阻挡材料的原子层，结合到阻挡材料层和导体芯的中间材料以及与中间材料结合的导体芯材料。导体芯与导体芯材料结合。

10. 发明申请

US20100261071A1 METALLIZED FIBERS FOR ELECTROCHEMICAL ENERGY STORAGE 审中-公开
标题翻译：用于电化学能量储存的金属化纤维
公开(公告)号：US20100261071A1
公开(公告)日：2010-10-14
申请号：US12759404
申请日：2010-04-13
申请人： Sergey D. Lopatin , Robert Z. Bachrach , Liang-Yuh Chen
发明人： Sergey D. Lopatin , Robert Z. Bachrach , Liang-Yuh Chen
IPC分类号： H01M6/02 , H01M4/02 , H01M6/00 , D01H13/30 , C25D17/00
CPC分类号： H01M4/66 , H01M4/133 , H01M4/366 , H01M4/587 , H01M4/626 , H01M4/661 , H01M4/667 , H01M10/0525 , Y10T29/49115
摘要： A cost effective method and apparatus are provided for forming metallized fibers and depositing multilayer films thereon to form thin film electrochemical energy storage devices. In one embodiment, a fibrous substrate is formed using a fiber spinning process and the fibrous substrate is plated with a copper layer using wet deposition. Multiple material layers are then deposited onto the copper layer to form a lithium-ion battery fiber.
摘要翻译：提供了一种成本有效的方法和装置，用于形成金属化纤维并在其上沉积多层膜以形成薄膜电化学能量存储装置。在一个实施例中，使用纤维纺丝工艺形成纤维基材，并且使用湿沉积将纤维基材镀铜层。然后将多个材料层沉积到铜层上以形成锂离子电池纤维。

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