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31. 发明授权

US5792672A Photoresist strip method 失效
标题翻译：光刻胶条法
公开(公告)号：US5792672A
公开(公告)日：1998-08-11
申请号：US618891
申请日：1996-03-20
申请人： Lap Chan , Simon Chooi Yen Meng , Tony Chan
发明人： Lap Chan , Simon Chooi Yen Meng , Tony Chan
IPC分类号： G03F7/42 , H01L21/311 , H01L21/465
CPC分类号： H01L21/31138 , G03F7/427
摘要： An improved method for removing a photoresist mask from an etched aluminum pattern after etching the pattern in a chlorine containing plasma has been created. The method is a two step process, in which a first stripping step is in a plasma containing O.sub.2 and H.sub.2 O and a second stripping step is in a plasma containing O.sub.2.
摘要翻译：已经产生了一种用于在含氯等离子体中蚀刻图案之后从蚀刻铝图案去除光致抗蚀剂掩模的改进方法。该方法是两步法，其中第一汽提步骤在含有O 2和H 2 O的等离子体中，第二汽提步骤在含有O 2的等离子体中。

32. 发明授权

US5744376A Method of manufacturing copper interconnect with top barrier layer 失效
标题翻译：制造具有顶部阻挡层的铜互连的方法
公开(公告)号：US5744376A
公开(公告)日：1998-04-28
申请号：US630709
申请日：1996-04-08
申请人： Lap Chan , Jia Zhen Zheng
发明人： Lap Chan , Jia Zhen Zheng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/28
CPC分类号： H01L21/76834 , H01L21/76843 , H01L23/53238 , H01L2924/0002
摘要： A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer ,while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
摘要翻译：描述了在集成电路中制造铜互连的结构和方法。该结构是镶嵌铜连接器，其上表面与嵌入其中的绝缘层的上表面共面。通过两个阻挡层防止铜从连接器的扩散。一个位于连接器和绝缘层之间的界面处，而第二屏障是覆盖连接器的上表面的绝缘层。镶嵌工艺包括用铜填充绝缘体表面的沟槽，然后通过化学去除多余的沟槽。抛光。由于光致抗蚀剂从不与铜直接接触，因此已经有效地消除了抗蚀剂灰化期间铜氧化的问题。

33. 发明授权

US5610083A Method of making back gate contact for silicon on insulator technology 失效
标题翻译：硅绝缘体技术的背栅接触方法
公开(公告)号：US5610083A
公开(公告)日：1997-03-11
申请号：US650697
申请日：1996-05-20
申请人： Lap Chan , Ravis H. Sundaresan , Che-Chia Wei
发明人： Lap Chan , Ravis H. Sundaresan , Che-Chia Wei
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203
摘要： A process for creating a back gate contact, in an SOI layer, that can easily be incorporated into a MOSFET fabrication recipe, has been developed. The back gate contact consists of a etched trench, lined with insulator, and filled with doped polysilicon. The polysilicon filled trench electrically connects the semiconductor substrate to overlying metal contacts.
摘要翻译：已经开发了用于在SOI层中产生可以容易地并入MOSFET制造配方中的背栅极接触的工艺。背栅极接触由蚀刻的沟槽组成，内衬绝缘体并填充有多晶硅。多晶硅填充沟槽将半导体衬底电连接到覆盖的金属触点。

34. 发明申请

US20120331036A1 System and Method of Enterprise Action Item Planning, Executing, Tracking and Analytics 有权
标题翻译：企业行动项目计划，执行，跟踪和分析的系统和方法
公开(公告)号：US20120331036A1
公开(公告)日：2012-12-27
申请号：US13166501
申请日：2011-06-22
申请人： Bin Duan , Lap Chan
发明人： Bin Duan , Lap Chan
IPC分类号： G06F15/16
CPC分类号： G06Q10/0631 , H04W64/006
摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.
摘要翻译：跟踪企业数据处理环境中的动作项目的系统和方法。该方法包括由客户端从服务器接收包括位置的动作项目。该方法还包括由客户端在与该动作项目相关的位置处执行登记。该方法还包括由客户端执行与该动作项目相关的退房。该方法还包括由客户端改变动作项目的状态。以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

35. 发明授权

US07382027B2 MOSFET device with low gate contact resistance 有权
标题翻译：具有低栅极接触电阻的MOSFET器件
公开(公告)号：US07382027B2
公开(公告)日：2008-06-03
申请号：US11045958
申请日：2005-01-28
申请人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
发明人： Purakh Raj Verma , Sanford Chu , Lap Chan , Yelehanka Pradeep , Kai Shao , Jia Zhen Zheng
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

36. 发明申请

US20070007623A1 Method to fabricate horizontal air columns underneath metal inductor 有权
标题翻译：在金属电感器下制造水平空气柱的方法
公开(公告)号：US20070007623A1
公开(公告)日：2007-01-11
申请号：US11519103
申请日：2006-09-11
申请人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L29/00
CPC分类号： H01L21/76834 , H01F3/14 , H01F17/0006 , H01F27/34 , H01F41/041 , H01F41/045 , H01L21/764 , H01L21/7682 , H01L23/5227 , H01L23/53295 , H01L27/08 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
摘要翻译：提供了一种在硅衬底的表面上形成电感器的新方法。本发明提供金属电感器下面的氧化物鳍片的覆盖层。氧化物鳍片为上覆的金属电感器提供了稳定的支持，同时也允许水平空气柱同时存在于电感器下面。通过重复施用所使用的掩模，可以在本发明的基础上产生空间上插入在所产生的氧化物翅片的覆盖层之间的空腔的覆盖层。衬底表面上的空穴的存在显着降低了与衬底相关联的电感器的寄生电容和串联电阻。

37. 发明授权

US06972237B2 Lateral heterojunction bipolar transistor and method of manufacture using selective epitaxial growth 有权
公开(公告)号：US06972237B2
公开(公告)日：2005-12-06
申请号：US10725670
申请日：2003-12-01
申请人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jia Zhen Zheng , Jian Xun Li
发明人： Purakh Raj Verma , Shao-fu Sanford Chu , Lap Chan , Jia Zhen Zheng , Jian Xun Li
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.

38. 发明申请

US20050136573A1 Method of making direct contact on gate by using dielectric stop layer 有权
标题翻译：通过使用介电阻挡层在栅极上直接接触的方法
公开(公告)号：US20050136573A1
公开(公告)日：2005-06-23
申请号：US11045958
申请日：2005-01-28
申请人： Purakh Rajverma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
发明人： Purakh Rajverma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

39. 发明申请

US20050124131A1 Method of forming an inductor with continuous metal deposition 审中-公开
标题翻译：形成具有连续金属沉积的电感器的方法
公开(公告)号：US20050124131A1
公开(公告)日：2005-06-09
申请号：US11034932
申请日：2005-01-13
申请人： Chit Hweing , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
发明人： Chit Hweing , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
IPC分类号： H01F17/00 , H01L21/02 , H01L23/522 , H01L21/20 , H01L29/00
CPC分类号： H01L28/10 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.
摘要翻译：描述了在硅衬底上制造RF电感器件的方法。沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。介电材料的第二层被沉积并图案化以形成通孔/沟槽。通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。这些沟槽用铜填充并平坦化。电介质膜的第三层被沉积并图案化以形成通孔/沟槽。然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。

40. 发明授权

US06903013B2 Method to fill a trench and tunnel by using ALD seed layer and electroless plating 有权
标题翻译：通过使用ALD种子层和化学镀填充沟槽和隧道的方法
公开(公告)号：US06903013B2
公开(公告)日：2005-06-07
申请号：US10439923
申请日：2003-05-16
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yong Ju , Jia Zhen Zheng
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yong Ju , Jia Zhen Zheng
IPC分类号： H01L21/285 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/28562 , H01L21/76843 , H01L21/76873 , H01L23/5227 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.
摘要翻译：已经开发了一种改进的方法，通过原子层沉积，ALD，用于化学镀铜的铜屏障和种子层，在镶嵌工艺中的填充沟槽和沟道或隧道开口，用于制造互连和电感器。概述本发明方法的工艺流程如下：（1）形成沟槽和通道，（2）铜屏障和晶种的原子层沉积，（3）铜的无电沉积，（4）化学机械抛光的过量铜，和（5）阻挡层沉积，SiN，形成铜互连和电感器。

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