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31. 发明授权

US6032170A Long instruction word controlling plural independent processor operations 失效
标题翻译：长指令字控制多个独立处理器操作
公开(公告)号：US6032170A
公开(公告)日：2000-02-29
申请号：US63318
申请日：1998-04-20
申请人： Karl M. Guttag , Christopher J. Read , Keith Balmer
发明人： Karl M. Guttag , Christopher J. Read , Keith Balmer
IPC分类号： G06F7/52 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F7/38
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus.
摘要翻译：一种数据处理装置，包括形成从每个N个N位的每两个数据总线的L位产生的乘积的乘数单元，其大于L.乘法器形成具有第一部分的N位输出，第一部分是产品和第二部分，M是不包括乘积的L个最低有效位的M个其他位，其中N是M和L的和。在优选实施例中，M个其他位从两个输入数据总线的其他位导出，例如第一输入数据总线的M个其他位。

32. 发明授权

US5768609A Reduced area of crossbar and method of operation 失效
标题翻译：横梁面积减小和作业方式
公开(公告)号：US5768609A
公开(公告)日：1998-06-16
申请号：US483657
申请日：1995-06-07
申请人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/17375
摘要： There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：已经公开了在一个实施例中将图像处理器和图形处理器设置为多处理器系统和方法。图像处理器被构造成具有几个单独的处理器，它们都具有到几个存储器的通信链路。交叉开关用于建立处理器存储器链路。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

33. 发明授权

US5734880A Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections 失效
标题翻译：硬件分支采用根据划分成多个部分的算术逻辑单元的部分的状态加载的循环控制寄存器
公开(公告)号：US5734880A
公开(公告)日：1998-03-31
申请号：US480230
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F15/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation. An arithmetic logic unit operation generates a status bit loaded into a status register or is split into sections and generates a status bit for each section stored in a multiple flags register (211) used to load the loop. count register. If this is zero then the loop priority logic reloads the program counter (701) with the loop start address and repeats the loop. If this is nonzero, program counter (701) may increment normally or will be loaded with the loop start address of a higher priority loop.
摘要翻译：条件硬件分支采用零开销循环逻辑并写入程序循环内的循环计数寄存器。零开销循环逻辑包括程序计数器（701），循环结束寄存器（711,712,713），循环开始寄存器（721,722,723），循环计数器寄存器（731,732,733），比较器（715， 716,717）和循环优先级逻辑（725）。通常，每个周期递增程序计数器（701）。比较器（715,716,717）将存储在程序计数器（701）中的地址与相应的循环结束寄存器（711,712,713）进行比较。如果程序计数器（701）中的地址等于循环结束地址，则循环优先级逻辑（725）递减循环计数寄存器，并加载循环起始寄存器中循环起始地址的程序计数器。硬件循环涉及在程序循环操作期间加载循环计数寄存器。算术逻辑单元操作产生加载到状态寄存器中的状态位或分割成部分，并且生成用于加载循环的多标志寄存器（211）中存储的每个部分的状态位。计数寄存器如果这是零，则循环优先级逻辑使用循环起始地址重新加载程序计数器（701）并重复循环。如果这是非零的，则程序计数器（701）可以正常地增加或将加载较高优先级循环的循环起始地址。

34. 发明授权

US5712999A Address generator employing selective merge of two independent addresses 失效
标题翻译：采用选择性合并两个独立地址的地址生成器
公开(公告)号：US5712999A
公开(公告)日：1998-01-27
申请号：US160114
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer
发明人： Karl M. Guttag , Keith Balmer
IPC分类号： G06F9/355 , G06F12/00 , G06F15/62
CPC分类号： G06F9/355
摘要： An address generator (120) forms a selective merge of two addresses. First (610) and second (620) address units generate respective first and second N bit address. Each unit (610, 620) preferrably includes a set of base address registers (611), a set of index address registers (612) and a full adder (615). Each address unit (610, 620) selects one of the base address registers (611) and one of the index address registers (612) according to the current instruction. The full adder (615) selectively adds the index address to the base address or subtracts the index address from the base addess according to the current instruction. An address multiplexer register (630) stores an N bit multiplex word. An address multiplexer (641) selects for each bit of the merged address from the first or second N bit address depending on the state of the corresponding bit of the multiplex word: An overflow detector (631, 633) generates an overflow signal when either the first address or the second address are beyond a predetermined range. The instruction may specify generation of the address regardless of overflow detection, aborting the address generation upon overflow detection or issuing a processor interrupt upon overflow detection. In the preferred embodiment of this invention, the address unit (120) is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
摘要翻译：地址生成器（120）形成两个地址的选择性合并。第一（610）和第二（620）地址单元产生相应的第一和第二N位地址。每个单元（610,620）优选地包括一组基地址寄存器（611），一组索引地址寄存器（612）和全加器（615）。每个地址单元（610,620）根据当前指令选择一个基地址寄存器（611）和一个索引地址寄存器（612）。全加器（615）选择性地将索引地址添加到基地址，或者根据当前指令从基地址中减去索引地址。地址多路复用器寄存器（630）存储N位复用字。地址多路复用器（641）根据多路复用字的相应位的状态从第一或第二N位地址中选择合并地址的每个位：溢出检测器（631,633）当产生溢出信号时第一地址或第二地址超出预定范围。该指令可以指定地址的生成，而不管溢出检测，溢出检测时中断地址生成或溢出检测时发出处理器中断。在本发明的优选实施例中，地址单元（120）被实现在至少一个数字图像/图形处理器（71,72,73,74）中，作为形成在使用的单个集成电路中的多处理器（100）的一部分在图像处理中。

35. 发明授权

US5371896A Multi-processor having control over synchronization of processors in mind mode and method of operation 失效
标题翻译：多处理器具有控制处理器同步的心态和操作方法
公开(公告)号：US5371896A
公开(公告)日：1994-12-06
申请号：US62867
申请日：1993-05-17
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/80 , G06F15/16
CPC分类号： G06F9/3885 , G06F15/8015 , G06F9/30087 , G06F9/3887
摘要： There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).
摘要翻译：公开了一种在一个实施例中将图像处理器作为图像处理器布置的多处理器系统。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路。包括各个处理器，交叉开关和存储器的整个图像处理器都包含在单个硅芯片上。每个处理器可以同时执行相同的指令（SIMD模式）或不同的指令（MIMD模式）。

36. 发明授权

US5239654A Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode 失效
标题翻译：在SIMD模式下工作时，双模SIMD / MIMD处理器提供MIMD指令存储器作为数据存储器的重用
公开(公告)号：US5239654A
公开(公告)日：1993-08-24
申请号：US437851
申请日：1989-11-17
申请人： Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove , Keith Balmer
发明人： Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove , Keith Balmer
IPC分类号： G06F9/30 , G06F9/302 , G06F9/315 , G06F9/32 , G06F9/38 , G06F13/376 , G06F15/173 , G06F15/80
CPC分类号： G06F9/30014 , G06F13/376 , G06F15/17375 , G06F15/8007 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/3842
摘要： A multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The multiprocessor system includes several individual processors all having communication links to several memories. Additional instruction memories are dedicated individually as cache memories to particular processors so that the processors can function in the multiple instruction, multiple data (MIMD) mode. When the processors function in the single instruction, multiple data mode (SIMD) the dedicated memories are reassigned for access by all of the processors for data. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：在一个实施例中，多处理器系统和方法被布置为图像和图形处理器。多处理器系统包括几个单独的处理器，它们都具有到几个存储器的通信链路。附加指令存储器单独专用作特定处理器的高速缓冲存储器，使得处理器可以在多指令，多数据（MIMD）模式中工作。当处理器在单指令中运行时，多数据模式（SIMD）专用存储器被重新分配用于所有处理器的数据访问。交叉开关用于建立处理器存储器链路。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

37. 发明授权

US5226125A Switch matrix having integrated crosspoint logic and method of operation 失效
标题翻译：具有集成交叉点逻辑和操作方法的开关矩阵
公开(公告)号：US5226125A
公开(公告)日：1993-07-06
申请号：US437875
申请日：1989-11-17
申请人： Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove
发明人： Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag , Robert J. Gove
IPC分类号： G06F13/14
CPC分类号： G06F13/14
摘要： There is disclosed a switch matrix and operational method relying upon a high degree of operational logic at each matrix crosspoint. In one embodiment, the switch is used in a multiprocessor system arranged as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. The switch matrix serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories and is contained on a single silicon substrate.
摘要翻译：公开了在每个矩阵交叉点依赖于高度的操作逻辑的开关矩阵和操作方法。在一个实施例中，开关用于被布置为图像和图形处理器的多处理器系统中。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。开关矩阵用于建立处理器存储器链路和整个图像处理器，包括各个处理器，交叉开关和存储器，并且被包含在单个硅衬底上。

38. 发明授权

US5212777A Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation 失效
标题翻译：单指令多数据（SIMD）和多指令多数据（MIMD）模式和操作方法可重配置多处理器
公开(公告)号：US5212777A
公开(公告)日：1993-05-18
申请号：US437858
申请日：1989-11-17
申请人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas K. Ing-Simmons , Karl M. Guttag
IPC分类号： G06F15/80
CPC分类号： G06F9/3885 , G06F15/8015 , G06F9/30087 , G06F9/3887
摘要： There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).
摘要翻译：公开了一种在一个实施例中将图像处理器作为图像处理器布置的多处理器系统。该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。交叉开关用于建立处理器存储器链路。包括单个处理器，交叉开关和存储器的整个图像处理器都包含在单个硅芯片上。每个处理器可以同时执行相同的指令（SIMD模式）或不同的指令（MIMD模式）。

39. 发明授权

US5197140A Sliced addressing multi-processor and method of operation 失效
标题翻译：切片寻址多处理器和操作方法
公开(公告)号：US5197140A
公开(公告)日：1993-03-23
申请号：US437946
申请日：1989-11-17
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F9/345 , G06F15/80 , G06T1/20
CPC分类号： G06F9/30036 , G06F15/8015 , G06F9/345 , G06T1/20
摘要： A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. An addressing scheme, called sliced addressing, is used to spread contiguous related data over several memories so that the data can be concurrently accessed by several processors. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
摘要翻译：在一个实施例中，多处理器系统被布置为图像和图形处理器。处理器的结构与几个单独的处理器都具有到几个存储器的通信链接。称为分片寻址的寻址方案用于在几个存储器上扩展连续的相关数据，以便可以由多个处理器同时访问数据。交叉开关用于建立处理器存储器链路。整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

40. 发明授权

US06948050B1 Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware 失效
标题翻译：单一集成电路体现了具有单独指令处理硬件的双异质处理器
公开(公告)号：US06948050B1
公开(公告)日：2005-09-20
申请号：US09875136
申请日：2001-06-06
申请人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
发明人： Robert J. Gove , Keith Balmer , Nicholas Kerin Ing-Simmons , Karl Marion Guttag
IPC分类号： G06F9/38 , G06F15/16 , G06F15/173
CPC分类号： G06F9/3885 , G06F9/3851 , G06F15/17375
摘要： A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.
摘要翻译：单个集成电路包括在不相交的程序和数据上独立操作的不同指令集上操作的第一和第二数据处理器。单个集成电路优选地包括外部接口，共享数据传输控制器和被分成多个可独立存取的存储体的共享存储器。两个数据处理器优选地是数字信号处理器（DSP）和精简指令集计算机（RISC）处理器。 DSP和RISC处理器被适当地编程以执行计算机图像处理的不同方面。

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