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    • 33. 发明授权
    • Film formation method and apparatus for semiconductor process
    • 用于半导体工艺的成膜方法和装置
    • US08080290B2
    • 2011-12-20
    • US12320018
    • 2009-01-14
    • Kazuhide HasebeNobutake NoderaMasanobu MatsunagaJun SatohPao-Hwa Chou
    • Kazuhide HasebeNobutake NoderaMasanobu MatsunagaJun SatohPao-Hwa Chou
    • H05H1/24C23C16/00
    • H01L21/3185C23C16/345C23C16/45542
    • A film formation method is used for forming a silicon nitride film on a target substrate by repeating a plasma cycle and a non-plasma cycle a plurality of times, in a process field configured to be selectively supplied with a first process gas containing a silane family gas and a second process gas containing a nitriding gas and communicating with an exciting mechanism for exciting the second process gas to be supplied. The method includes obtaining a relation formula or relation table that represents relationship of a cycle mixture manner of the plasma cycle and the non-plasma cycle relative to a film quality factor of the silicon nitride film; determining a specific manner of the cycle mixture manner based on a target value of the film quality factor with reference to the relation formula or relation table; and arranging the film formation process in accordance with the specific manner.
    • 使用成膜方法在目标衬底上形成氮化硅膜,通过重复等离子体循环和非等离子体循环多次,在被配置为选择性地供给包含硅烷族的第一工艺气体的工艺过程中 气体和含有氮化气体的第二工艺气体,并与用于激发待供应的第二工艺气体的激励机构连通。 该方法包括获得表示等离子体循环与非等离子体循环的循环混合方式相对于氮化硅膜的膜质量因子的关系的关系式或关系表; 参照关系公式或关系表,基于电影品质因子的目标值确定循环混合方式的具体方式; 并根据具体方式布置成膜处理。
    • 38. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US07718497B2
    • 2010-05-18
    • US12130296
    • 2008-05-30
    • Yasushi AkasakaNoriaki FukiageYoshihiro KatoKazuhide HasebePao-Hwa Chou
    • Yasushi AkasakaNoriaki FukiageYoshihiro KatoKazuhide HasebePao-Hwa Chou
    • H01L21/8234
    • H01L21/823864H01L21/823814
    • A semiconductor device manufacturing method includes: forming a sidewall spacer on a sidewall surface of a gate electrode; forming a pair of second conductive type source and drain regions in an active region; covering top surfaces of a semiconductor layer, a device isolation region, the sidewall spacer and the gate electrode with a metal film; reducing resistance of the source and drain regions and the gate electrode partially by making the metal film react with the semiconductor layer and the gate electrode; and removing an unreacted portion of the metal film and the sidewall spacer simultaneously by using an etchant which readily etches the unreacted portion of the metal film and the sidewall spacer while hardly etching the device isolation region, resistance-reduced portions of the gate electrode and resistance-reduced portions of the source and drain regions.
    • 半导体器件制造方法包括:在栅电极的侧壁表面上形成侧壁间隔物; 在有源区中形成一对第二导电型源区和漏区; 用金属膜覆盖半导体层的顶表面,器件隔离区,侧壁间隔物和栅电极; 通过使金属膜与半导体层和栅极电极反应,部分地降低源极和漏极区域和栅电极的电阻; 并且通过使用易于蚀刻金属膜和侧壁间隔物的未反应部分的蚀刻剂同时去除金属膜和侧壁间隔物的未反应部分,同时几乎不蚀刻器件隔离区域,栅电极的电阻减少部分和电阻 - 源区和漏区的部分。
    • 39. 发明申请
    • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • US20080299728A1
    • 2008-12-04
    • US12130296
    • 2008-05-30
    • Yasushi AkasakaNoriaki FukiageYoshihiro KatoKazuhide HasebePao-Hwa Chou
    • Yasushi AkasakaNoriaki FukiageYoshihiro KatoKazuhide HasebePao-Hwa Chou
    • H01L21/8236
    • H01L21/823864H01L21/823814
    • A semiconductor device manufacturing method includes: forming a sidewall spacer on a sidewall surface of a gate electrode; forming a pair of second conductive type source and drain regions in an active region; covering top surfaces of a semiconductor layer, a device isolation region, the sidewall spacer and the gate electrode with a metal film; reducing resistance of the source and drain regions and the gate electrode partially by making the metal film react with the semiconductor layer and the gate electrode; and removing an unreacted portion of the metal film and the sidewall spacer simultaneously by using an etchant which readily etches the unreacted portion of the metal film and the sidewall spacer while hardly etching the device isolation region, resistance-reduced portions of the gate electrode and resistance-reduced portions of the source and drain regions.
    • 半导体器件制造方法包括:在栅电极的侧壁表面上形成侧壁间隔物; 在有源区中形成一对第二导电型源区和漏区; 用金属膜覆盖半导体层的顶表面,器件隔离区,侧壁间隔物和栅电极; 通过使金属膜与半导体层和栅极电极反应,部分地降低源极和漏极区域和栅电极的电阻; 并且通过使用易于蚀刻金属膜和侧壁间隔物的未反应部分的蚀刻剂同时去除金属膜和侧壁间隔物的未反应部分,同时几乎不蚀刻器件隔离区域,栅电极的电阻减少部分和电阻 - 源区和漏区的部分。