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31. 发明授权

US08283263B2 Integrated circuit system including nitride layer technology 有权
标题翻译：集成电路系统包括氮化层技术
公开(公告)号：US08283263B2
公开(公告)日：2012-10-09
申请号：US11428618
申请日：2006-07-05
申请人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
发明人： Sripad Sheshagiri Nagarad , Hwa Weng Koh , Dong Kyun Sohn , Xiaoyu Chen , Louis Lim , Sung Mun Jung , Chiew Wah Yap , Pradeep Ramachandramurthy Yelehanka , Nitin Kamat
IPC分类号： H01L21/469
CPC分类号： H01L21/3185 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.
摘要翻译：一种用于制造集成电路系统的集成电路方法，该集成电路系统包括将晶片装载到处理室中并用第一氨气预处理室。在晶片上沉积第一氮化物层并用第二氨气吹扫处理室。在与第一氮化物层不对准的第一氮化物层上沉积第二氮化物层。用第三氨气对处理室进行后吹扫，并用氮气吹扫处理室。

32. 发明授权

US07332378B2 Integrated circuit memory system with dummy active region 有权
标题翻译：具有虚拟有源区的集成电路存储器系统
公开(公告)号：US07332378B2
公开(公告)日：2008-02-19
申请号：US11308061
申请日：2006-03-04
申请人： Sung Mun Jung , Ching Dong Wang , Louis Yoke Leng Lim , Swee Tuck Woo , Donghua Liu , Xiaoyu Chen
发明人： Sung Mun Jung , Ching Dong Wang , Louis Yoke Leng Lim , Swee Tuck Woo , Donghua Liu , Xiaoyu Chen
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , H01L27/11568
摘要： An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.
摘要翻译：一种集成电路存储器系统，包括形成有等间隔开的浅沟槽隔离区域的衬底。在等离子间隔开的浅沟槽隔离区域之间的衬底内形成有源区和虚拟有源区。在活跃区域内形成源头和排水渠。提供在第一方向上延伸的字线和源极线，并且沿第二方向延伸的位线。在虚拟有源区域上形成接触区域，用于将字线和源极线捆扎到位线。

33. 发明授权

US07195977B2 Method for fabricating a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07195977B2
公开(公告)日：2007-03-27
申请号：US10954484
申请日：2004-10-01
申请人： Sung Mun Jung , Dong Oog Kim
发明人： Sung Mun Jung , Dong Oog Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/26586
摘要： A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions; etching the gate oxide lines and the field oxide regions between the gate lines; and forming a self-aligned source (SAS) region by injecting impurity ions into the etched regions, the impurity ion being injected in a direction at a predetermined angle other than 90° relative to the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成线性场氧化物区域; 在所述场氧化物区域之间的所述半导体衬底上形成栅极氧化物线; 在场氧化物区域和栅极氧化物线上形成栅极线，栅极线基本上垂直于场氧化物区域; 蚀刻栅极线之间的栅极氧化物线和场氧化物区域; 以及通过将杂质离子注入蚀刻区域而形成自对准源（SAS）区域，杂质离子以相对于半导体衬底的90°以外的预定角度的方向注入。

34. 发明授权

US06642110B2 Flash memory cell and method of manufacturing the same 失效
公开(公告)号：US06642110B2
公开(公告)日：2003-11-04
申请号：US10224561
申请日：2002-08-21
申请人： Sung Mun Jung , Sung Bo Sim , Kwi Wook Kim
发明人： Sung Mun Jung , Sung Bo Sim , Kwi Wook Kim
IPC分类号： H01L218247
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42324
摘要： There is disclosed a flash memory cell and method of manufacturing the same, in which the circular hole is formed in the insulating film formed on the silicon substrate, the floating gate having a cylindrical shape is formed within the hole and the control gate is formed within the floating gate. Therefore, the source used as a current supply and the silicon substrate may be formed integratedly, and also the process of forming a device separation film can be omitted, thus allowing manufacturing an ultra high integration nonvolatile memory device.

35. 发明授权

US06465833B1 Flash memory cell and method of manufacturing 失效
标题翻译：闪存单元和制造方法
公开(公告)号：US06465833B1
公开(公告)日：2002-10-15
申请号：US09474371
申请日：1999-12-29
申请人： Sung Mun Jung , Sung Bo Sim , Kwi Wook Kim
发明人： Sung Mun Jung , Sung Bo Sim , Kwi Wook Kim
IPC分类号： H01L2976
CPC分类号： H01L29/7883 , H01L21/28273 , H01L29/42324
摘要： There is disclosed a flash memory cell and method of manufacturing the same, in which the circular hole is formed in the insulating film formed on the silicon substrate, the floating gate having a cylindrical shape is formed within the hole and the control gate is formed within the floating gate. Therefore, the source used as a current supply and the silicon substrate may be formed integratedly, and also the process of forming a device separation film can be omitted, thus allowing manufacturing an ultra high integration non-volatile memory device.
摘要翻译：公开了一种闪存单元及其制造方法，其中在形成在硅衬底上的绝缘膜中形成圆形孔，在孔内形成具有圆柱形状的浮动栅极，并且在该栅极内部形成控制栅极浮动门。因此，用作电流源的源和硅衬底可以一体地形成，并且也可以省略形成器件分离膜的工艺，从而可以制造超高集成度的非易失性存储器件。

36. 发明授权

US06426897B1 Method of erasing a flash memory device 失效
标题翻译：擦除闪存设备的方法
公开(公告)号：US06426897B1
公开(公告)日：2002-07-30
申请号：US09721936
申请日：2000-11-27
申请人： Sung Mun Jung , Hee Gee Lee , Soo Min Cho
发明人： Sung Mun Jung , Hee Gee Lee , Soo Min Cho
IPC分类号： G11C1604
CPC分类号： G11C16/16
摘要： A method of erasing a flash memory device performs erase operation by hot carrier injection method, by applying a ground potential to a source and applying the bias from a high voltage to a low voltage step by step, with a voltage of 5V being applied to a drain, wherein the bias of a floating gate in the flash memory device keeps 1.8 through 2V. being hot carrier injection condition and wherein the gate bias adjusts the bias applied according to the coupling ratio. Thus, it can reduce the erase time and allows the erase on a byte basis.
摘要翻译：一种擦除闪速存储器件的方法是通过向源极施加接地电位并且将偏压从高电压逐步施加到低电压来执行通过热载流子注入方法的擦除操作，其中5V的电压施加到漏极，其中闪存器件中的浮置栅极的偏置保持1.8至2V。是热载流子注入条件，其中栅极偏置根据耦合比来调整施加的偏压。因此，它可以减少擦除时间并允许以字节为单位的擦除。

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