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31. 发明授权

US06956417B2 Leakage compensation circuit 失效
标题翻译：漏电补偿电路
公开(公告)号：US06956417B2
公开(公告)日：2005-10-18
申请号：US10707123
申请日：2003-11-21
申请人： Kerry Bernstein , Anthony R. Bonaccio , John A. Fifield , Allen P. Haar , Shiu C. Ho , Terence B. Hook , Michael A. Soma , Stephen D. Wyatt
发明人： Kerry Bernstein , Anthony R. Bonaccio , John A. Fifield , Allen P. Haar , Shiu C. Ho , Terence B. Hook , Michael A. Soma , Stephen D. Wyatt
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093
CPC分类号： H03L7/093 , H03L7/0891
摘要： A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.
摘要翻译：一种电路，包括：电容器，耦合在第一电路节点和第二电路节点之间，并且泄漏电流从第一电路节点泄漏到第二电路节点; 以及补偿电路，其适于提供补偿电流以补偿到第一电路节点的漏电流。

32. 发明授权

US06927616B2 Integrated circuit and method for interfacing two voltage domains using a transformer 失效
标题翻译：使用变压器连接两个电压域的集成电路和方法
公开(公告)号：US06927616B2
公开(公告)日：2005-08-09
申请号：US10605855
申请日：2003-10-31
申请人： Shiu Chung Ho , Ivan L. Wemple , Stephen D. Wyatt
发明人： Shiu Chung Ho , Ivan L. Wemple , Stephen D. Wyatt
IPC分类号： H01L27/02 , H03K17/691 , H03K19/0175 , G06F1/04
CPC分类号： H03K19/017545 , H01L27/0251 , H03K17/691
摘要： An integrated circuit designed to reduce on-chip noise coupling. In one embodiment, circuit (60) includes the following: a circuit transformer (62) capable of converting a noise sensitive input reference clock signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and a biased receiver network (64) having a PFET current mirror (74) coupled with a NFET current (72), the biased receiver transistor network designed to multiply the transformer signal to offset a mutual coupling loss of the transformer. In at least one alternative embodiment, the input reference clock signal originates at an off-chip clock generator circuit (42) and the output signal from receiver (64) is input to a PLL (44). In another alternative embodiment, the transformer is a monolithic integrated transformer. Another alternative embodiment of the present invention is a method of reducing on-chip noise coupling.
摘要翻译：一种集成电路，旨在减少片内噪声耦合。在一个实施例中，电路（60）包括以下：电路变压器（62），其能够将噪声敏感的输入参考时钟信号转换成具有与预定接收电压逻辑电平兼容的电压的输出信号; 以及偏置的接收器网络（64），其具有与NFET电流（72）耦合的PFET电流镜（74），所述偏置的接收器晶体管网络被设计为将变压器信号乘以偏移变压器的互耦合损耗。在至少一个备选实施例中，输入参考时钟信号起始于片外时钟发生器电路（42），并且来自接收机（64）的输出信号被输入到PLL（44）。在另一替代实施例中，变压器是单片集成变压器。本发明的另一替代实施例是减少片上噪声耦合的方法。

33. 发明授权

US06825490B1 On chip resistor calibration structure and method 失效
标题翻译：片上电阻校准结构及方法
公开(公告)号：US06825490B1
公开(公告)日：2004-11-30
申请号：US10605567
申请日：2003-10-09
申请人： Terence B. Hook , Raminderpal Singh , Stephen D. Wyatt
发明人： Terence B. Hook , Raminderpal Singh , Stephen D. Wyatt
IPC分类号： H01L2358
CPC分类号： G01R35/005
摘要： A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.
摘要翻译：确定半导体器件内校准电阻器的实际电阻值的结构和相关方法。半导体器件包括电容器，校准电阻器和校准电路。施加到校准电阻器的电压产生通过校准电阻器的电流，以对电容器充电。校准电路适于测量对电容器充电所需的实际时间。校准电路还适用于根据电容器充电所需的实际时间和电容器的电容值来计算校准电阻器的实际电阻值。

34. 发明授权

US5525932A Lock indicator for phase locked loop circuit 失效
标题翻译：锁相环电路锁定指示灯
公开(公告)号：US5525932A
公开(公告)日：1996-06-11
申请号：US298621
申请日：1994-08-31
申请人： Ram Kelkar , Iiya I. Novof , Stephen D. Wyatt
发明人： Ram Kelkar , Iiya I. Novof , Stephen D. Wyatt
IPC分类号： H03L7/089 , H03L7/093 , H03L7/095 , H03L7/10
CPC分类号： H03L7/095 , H03L7/0893 , H03L7/0896 , Y10S331/02
摘要： A phase locked loop circuit which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone" is provided. A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.
摘要翻译：提供了一种锁相环电路，其包括使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲的相位/频率检测器。一对电荷泵接收INC和DEC脉冲。一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。通过该电荷泵将差分电流输出到环路滤波电容器。另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

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