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31. 发明授权

US06867130B1 Enhanced silicidation of polysilicon gate electrodes 有权
标题翻译：增强多晶硅栅电极的硅化
公开(公告)号：US06867130B1
公开(公告)日：2005-03-15
申请号：US10445936
申请日：2003-05-28
申请人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
发明人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28114 , H01L21/28518 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.
摘要翻译：通过在栅极电极和源极/漏极区域上形成薄金属硅化物层，然后选择性地使栅电极重新硅化，来制造在源极/漏极区域中显示出降低的栅极电阻和减少的硅化物尖峰的半导体器件。实施例包括在多晶硅栅极电极和源极/漏极区域上形成薄金属硅化物层，通过高密度等离子体沉积沉积介电间隙填充层，回蚀刻以选择性地暴露硅化多晶硅栅电极并使多晶硅栅电极重新硅化增加其上的金属硅化物层的厚度。实施例还包括重新硅化多晶硅栅电极，其包括形成蘑菇状金属硅化物层的上侧表面的一部分。

32. 发明授权

US06689688B2 Method and device using silicide contacts for semiconductor processing 失效
标题翻译：使用半导体处理硅化物触点的方法和器件
公开(公告)号：US06689688B2
公开(公告)日：2004-02-10
申请号：US10180858
申请日：2002-06-25
申请人： Paul Raymond Besser , Simon S. Chan , David E. Brown , Eric Paton
发明人： Paul Raymond Besser , Simon S. Chan , David E. Brown , Eric Paton
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： A method for forming silicide contacts includes forming a layer on silicon-containing active device regions such as source, drain, and gate regions. The layer contains a metal that is capable of forming one or more metal silicides and a material that is soluble in a first metal silicide but not soluble in a second metal silicide, or is more soluble in the first metal silicide than in the second metal silicide. The layer may be formed by vapor deposition methods such as physical vapor deposition, chemical vapor deposition, evaporation, laser ablation, or other deposition method. A method for forming silicide contacts includes forming a metal layer, then implanting the metal layer and/or underlying silicon layer with a material such as that described above. The material may be implanted in the silicon layer prior to formation of the metal layer. Contacts formed include a first metal silicide and a material that is more soluble in a first metal silicide than in a second metal silicide. The contacts may be part of a semiconductor device including a substrate, active region containing silicon, and silicide contacts disposed over the active region and capable of electrically coupling the active region to other regions such as metallization lines.
摘要翻译：用于形成硅化物接触的方法包括在诸如源极，漏极和栅极区域的含硅有源器件区域上形成层。该层包含能够形成一种或多种金属硅化物的金属和可溶于第一金属硅化物但不溶于第二金属硅化物的材料，或者比第二金属硅化物更可溶于第一金属硅化物。该层可以通过诸如物理气相沉积，化学气相沉积，蒸发，激光烧蚀或其它沉积方法之类的气相沉积方法形成。形成硅化物接触的方法包括形成金属层，然后用如上所述的材料注入金属层和/或下层硅层。在形成金属层之前，材料可以被植入到硅层中。形成的触点包括第一金属硅化物和在第一金属硅化物中比在第二金属硅化物中更可溶的材料。触点可以是半导体器件的一部分，其包括衬底，含硅的有源区和设置在有源区上的硅化物触点，并且能够将有源区电耦合到诸如金属化线的其它区域。

33. 发明授权

US06258683B1 Local interconnection arrangement with reduced junction leakage and method of forming same 有权
标题翻译：具有减少结漏的局部互连布置及其形成方法
公开(公告)号：US06258683B1
公开(公告)日：2001-07-10
申请号：US09477741
申请日：2000-01-05
申请人： Paul Besser , Simon S. Chan , Yowjuang Bill Liu
发明人： Paul Besser , Simon S. Chan , Yowjuang Bill Liu
IPC分类号： H01L21336
CPC分类号： H01L23/485 , H01L21/76895 , H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A method and arrangement for forming a local interconnect without etching completely through a junction and causing device shorts introduces an additional ion implantation step following the etching of the local interconnect opening into the substrate. The additional ion implantation step into the active region ensures that the depth of the junction is below the depth reached by the local interconnect opening and the substrate.
摘要翻译：用于形成局部互连而不是完全蚀刻通过结而导致器件短路的局部互连的方法和装置在蚀刻到衬底中的局部互连开口之后引入额外的离子注入步骤。进入有源区域的附加离子注入步骤确保结的深度低于局部互连开口和衬底达到的深度。

34. 发明授权

US06251776B1 Plasma treatment to reduce stress corrosion induced voiding of patterned metal layers 有权
标题翻译：等离子体处理以减少应力腐蚀导致图案化金属层的排空
公开(公告)号：US06251776B1
公开(公告)日：2001-06-26
申请号：US09283754
申请日：1999-04-02
申请人： Minh Van Ngo , Simon S. Chan , Anne E. Sanderfer , King Wai Kelwin Ko
发明人： Minh Van Ngo , Simon S. Chan , Anne E. Sanderfer , King Wai Kelwin Ko
IPC分类号： H01L21441
CPC分类号： H01L21/02071 , H01L21/02052 , H01L21/02054 , H01L21/76838
摘要： Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a plasma containing ammonia or ammonia and oxygen at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDP CVD.
摘要翻译：通过在间隙填充之前去除蚀刻残留物来避免或显着减少图形化金属层的应力腐蚀引起的空隙。实施例包括使用氟和/或氯化学，湿洗，用至少约400℃的温度下含有氨或氨和等离子体的等离子体进行蚀刻Al或Al合金层，以及填充介电材料的间隙。 HDP CVD的HDP氧化物。

35. 发明授权

US06171919B2 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation 有权
标题翻译： MOS晶体管形成工艺包括用于改善硅化物形成的后间隔蚀刻表面处理
公开(公告)号：US06171919B2
公开(公告)日：2001-01-09
申请号：US09361155
申请日：1999-07-27
申请人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
发明人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣。实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

36. 发明授权

US5861677A Low RC interconnection 失效
标题翻译：低RC互连
公开(公告)号：US5861677A
公开(公告)日：1999-01-19
申请号：US890905
申请日：1997-07-10
申请人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Lu You , Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/3205 , H01L21/312 , H01L21/768 , H01L23/31 , H01L23/52 , H01L23/522 , H01L23/532 , B29B13/00 , B05D3/02 , H01L21/283
CPC分类号： H01L23/3142 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/12044
摘要： A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.
摘要翻译：低阻抗延迟互连图案由诸如铜的低电阻率金属和诸如有机聚合物的低介电常数材料形成。在使用粘合促进剂的低电阻率金属和低介电常数材料之间形成中间粘合层，例如硅烷类粘合促进剂。粘合促进剂可以施加在金属和电介质层之间或并入电介质层中。

37. 发明授权

US5670828A Tunneling technology for reducing intra-conductive layer capacitance 失效
标题翻译：用于降低导电层电容的隧道技术
公开(公告)号：US5670828A
公开(公告)日：1997-09-23
申请号：US391692
申请日：1995-02-21
申请人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
发明人： Robin W. Cheung , Simon S. Chan , Richard J. Huang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002
摘要： The control speed of semiconductor circuitry is increased by forming air tunnels in the interwiring spaces of a conductive pattern to reduce intra-conductive layer capacitance.
摘要翻译：通过在导电图案的布线间隙中形成空气隧道以减少导电层电容来增加半导体电路的控制速度。

38. 发明授权

US4978639A Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips 失效
标题翻译：在半导体芯片上同时形成通孔和环绕电镀的方法
公开(公告)号：US4978639A
公开(公告)日：1990-12-18
申请号：US295300
申请日：1989-01-10
申请人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan S. Day , Adrian C. Lee
发明人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan S. Day , Adrian C. Lee
IPC分类号： H01L21/288 , H01L21/768
CPC分类号： H01L21/78 , H01L21/288 , H01L21/76898 , Y10S148/028 , Y10S148/135 , Y10S438/977
摘要： Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.
摘要翻译：在半导体芯片上同时形成金属化的通孔和环绕的金属电镀，方法是在晶片的前表面上形成光致抗蚀剂掩模以在金属焊盘上打开窗口以及需要环绕电镀的栅格区域; 如果需要则蚀刻暴露的金属，并通过反应离子蚀刻在晶片中形成通孔和沟槽，其深度小于晶片的总厚度; 通过化学镀方法沿沟槽和通孔的壁沉积薄导电膜; 通过电解方法用导电金属电镀槽和通孔; 与两个槽和通孔的地板一起去除晶片的背面（“后退”），以露出通孔壁上的金属并分离各个芯片; 并且在各个芯片的背面上沉积导电金属，以完成接地路径。

39. 发明授权

US08617983B2 Local interconnect having increased misalignment tolerance 有权
标题翻译：本地互连具有增加的不对准公差
公开(公告)号：US08617983B2
公开(公告)日：2013-12-31
申请号：US13608698
申请日：2012-09-10
申请人： Simon S. Chan
发明人： Simon S. Chan
IPC分类号： H01L21/4763
CPC分类号： H01L27/11568 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.
摘要翻译：提供一种用于在半导体存储器件中形成互连的方法。该方法包括在衬底上形成一对源极选择晶体管。源区域形成在一对源极选择晶体管之间的衬底中。在所述一对源极选择晶体管之间形成第一层间电介质。掩模层沉积在一对源极选择晶体管和层间电介质上，其中掩模层限定了一对源极选择晶体管之间的局部互连区域，其宽度小于一对源选择晶体管之间的距离。蚀刻半导体存储器件以去除局部互连区域中的第一层间电介质的一部分，从而暴露源极区域。在局部互连区域中形成金属接触。

40. 发明授权

US08236693B2 Methods of forming silicides of different thicknesses on different structures 有权
标题翻译：在不同结构上形成不同厚度的硅化物的方法
公开(公告)号：US08236693B2
公开(公告)日：2012-08-07
申请号：US11748743
申请日：2007-05-15
申请人： Wen Yu , Paul Besser , Bin Yang , Haijiang Yu , Simon S. Chan
发明人： Wen Yu , Paul Besser , Bin Yang , Haijiang Yu , Simon S. Chan
IPC分类号： H01L21/44
CPC分类号： H01L21/324 , H01L21/28052 , H01L29/66507 , H01L29/78
摘要： The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.
摘要翻译：形成器件的栅极和有源区，并且施加和去除氮化物和氧化物层的交替步骤允许在不同区域暴露硅，同时保持覆盖有氮化物的其它区域中的硅或多晶硅。金属层沉积在暴露的硅或多晶硅上，退火在所选择的暴露区域中形成硅化物层。氧化物层和/或氮化物层从被覆盖区域移除，另一个金属层被沉积。在第二暴露区域上形成一层厚度的硅化物，并在先前的硅化物厚度上形成附加的硅化物厚度来重复退火工艺。

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