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1. 发明授权

US4978639A Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips 失效
标题翻译：在半导体芯片上同时形成通孔和环绕电镀的方法
公开(公告)号：US4978639A
公开(公告)日：1990-12-18
申请号：US295300
申请日：1989-01-10
申请人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan S. Day , Adrian C. Lee
发明人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan S. Day , Adrian C. Lee
IPC分类号： H01L21/288 , H01L21/768
CPC分类号： H01L21/78 , H01L21/288 , H01L21/76898 , Y10S148/028 , Y10S148/135 , Y10S438/977
摘要： Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.
摘要翻译：在半导体芯片上同时形成金属化的通孔和环绕的金属电镀，方法是在晶片的前表面上形成光致抗蚀剂掩模以在金属焊盘上打开窗口以及需要环绕电镀的栅格区域; 如果需要则蚀刻暴露的金属，并通过反应离子蚀刻在晶片中形成通孔和沟槽，其深度小于晶片的总厚度; 通过化学镀方法沿沟槽和通孔的壁沉积薄导电膜; 通过电解方法用导电金属电镀槽和通孔; 与两个槽和通孔的地板一起去除晶片的背面（“后退”），以露出通孔壁上的金属并分离各个芯片; 并且在各个芯片的背面上沉积导电金属，以完成接地路径。

2. 发明授权

US4808273A Method of forming completely metallized via holes in semiconductors 失效
标题翻译：在半导体中形成完全金属化的通孔的方法
公开(公告)号：US4808273A
公开(公告)日：1989-02-28
申请号：US192343
申请日：1988-05-10
申请人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
发明人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
IPC分类号： H01L21/74 , H01L21/768 , C25D5/02
CPC分类号： H01L21/76898
摘要： A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.
摘要翻译：公开了一种用于在半导体晶片中形成完全金属化的通孔的方法。金属焊盘与导电互连网络一起形成在半导体晶片的一个面上。然后沉积绝缘层以覆盖晶片的这个面。孔在晶片的相对表面被蚀刻，直至并暴露出金属焊盘的一部分。然后使用金属垫作为阴极，通过电镀将通孔用金属完全填充。

3. 发明授权

US4842699A Method of selective via-hole and heat sink plating using a metal mask 失效
标题翻译：使用金属掩模的选择性通孔和散热电镀方法
公开(公告)号：US4842699A
公开(公告)日：1989-06-27
申请号：US192199
申请日：1988-05-10
申请人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
发明人： Chang-Hwang Hua , Ding-Yuan S. Day , Simon S. Chan
IPC分类号： C25D5/02 , H01L21/768 , H01L23/48
CPC分类号： C25D5/022 , H01L21/76898 , H01L23/481 , H01L2924/0002
摘要： A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;(c) forming via-holes through said wafer;(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.
摘要翻译：一种使用金属掩模同时选择性地电镀与半导体晶片相关的通孔和散热器的方法，包括以下步骤：（a）用绝缘层涂覆晶片的第一侧以防止在该第一侧上的电镀; （b）在晶片的与第一侧相对的第二面上图案化，用于限定不应发生电镀的区域的金属掩模; （c）通过所述晶片形成通孔; （d）沉积薄的导电膜以覆盖通孔的底部和壁以及未被金属掩模覆盖的晶片的第二面的区域; 和（e）如果需要的话，对所得的晶片进行电解电镀，同时超声波地搅动电解质，以确保足够的电解质输送到通孔中用于均匀的电镀。

4. 发明授权

US5288660A Method for forming self-aligned t-shaped transistor electrode 失效
标题翻译：用于形成自对准t形晶体管电极的方法
公开(公告)号：US5288660A
公开(公告)日：1994-02-22
申请号：US11998
申请日：1993-02-01
申请人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan Day
发明人： Chang-Hwang Hua , Simon S. Chan , Ding-Yuan Day
IPC分类号： H01L21/027 , H01L21/768 , H01L21/283 , H01L21/312
CPC分类号： H01L21/76802 , H01L21/0274
摘要： A T-shaped electrode is formed on a semiconductor substrate by first forming a dielectric film on the substrate. A first layer of photoresist is applied on the upper surface of the dielectric film, and a second layer of photoresist is applied over the first layer of photoresist. The first and second layers of photoresist have different optical properties, requiring different wavelengths of ultraviolet for exposure before developing. Portions of the first and second photoresist layers and the dielectric film are selectively removed by photolithographic techniques with one masking step for forming an opening to the substrate. The first and second photoresist layers adjacent to the opening are ion etched to expose the upper surface of the dielectric film adjacent to the opening. A portion of the first photoresist layer adjacent to the opening is removed to undercut the second photoresist layer. Metal is deposited in the opening and on the exposed upper surface of the dielectric film to form a T-shaped electrode. The first and second photoresist layers are then removed, thereby also removing metal deposited on top of the second layer of photoresist.
摘要翻译：首先在基板上形成电介质膜，在半导体基板上形成T字形电极。在电介质膜的上表面上施加第一层光致抗蚀剂，在第一层光致抗蚀剂上施加第二层光致抗蚀剂。第一层和第二层光致抗蚀剂具有不同的光学性质，在显影之前需要不同波长的紫外线进行曝光。通过光刻技术选择性地去除第一和第二光致抗蚀剂层和电介质膜的部分，其中一个掩模步骤用于形成对该基底的开口。邻近开口的第一和第二光致抗蚀剂层被离子蚀刻以暴露与开口相邻的电介质膜的上表面。去除与开口相邻的第一光致抗蚀剂层的一部分以切割第二光致抗蚀剂层。金属沉积在介质膜的开口和暴露的上表面上以形成T形电极。然后去除第一和第二光致抗蚀剂层，从而也去除沉积在第二层光致抗蚀剂上的金属。

5. 发明授权

US08497206B2 Method of processing backside copper layer for semiconductor chips 有权
标题翻译：处理半导体芯片背面铜层的方法
公开(公告)号：US08497206B2
公开(公告)日：2013-07-30
申请号：US12757458
申请日：2010-04-09
申请人： Chang-Hwang Hua , Wen Chu
发明人： Chang-Hwang Hua , Wen Chu
IPC分类号： H01L21/441 , H01L29/41
CPC分类号： H01L21/76898 , H01L21/76849 , H01L21/76873 , H01L21/78 , H01L23/481 , H01L29/0657 , H01L29/41708 , H01L29/41725 , H01L2924/0002 , H01L2924/00
摘要： A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.
摘要翻译：公开了一种用于半导体芯片的铜背面金属层的处理方法。已经制造在前侧的电子器件的半导体晶片的背面首先通过化学镀或溅射涂覆有薄金属种子层。然后，将铜背面金属层涂覆在金属籽晶层上。金属种子层不仅通过背面通孔增加了前侧金属层和铜背面金属层之间的粘附性，而且还防止了后续制造工艺中的半导体基板的金属剥离，这有助于提高器件性能的可靠性。用于金属种子层的合适材料包括Pd，Au，Ni，Ag，Co，Cr，Pt或它们的合金，例如NiP，NiB，AuSn，Pt-Rh等。使用Pd作为种子层对于铜背面金属层特别有用，因为Pd层还用作扩散阻挡层以防止Cu原子进入半导体晶片。

6. 发明授权

US08033011B2 Method for mounting a thinned semiconductor wafer on a carrier substrate 有权
标题翻译：将减薄的半导体晶片安装在载体基板上的方法
公开(公告)号：US08033011B2
公开(公告)日：2011-10-11
申请号：US12222343
申请日：2008-08-07
申请人： Jason Chou , Chang-Hwang Hua , Ping-Wei Chen , Sen Yang
发明人： Jason Chou , Chang-Hwang Hua , Ping-Wei Chen , Sen Yang
IPC分类号： H01L21/70
CPC分类号： H01L21/187 , H01L31/0392 , H01L31/1896 , Y02E10/50 , Y10T29/49126 , Y10T29/4913
摘要： A method for mounting a thinned semiconductor wafer on a carrier substrate for further processing is disclosed. The method consists of a series of steps, which is based on providing a frame with a double-side tape to mount the thinned wafer on the carrier substrate. The frame is used to support the double-side tape and can be designed to fit the conventional production line for holding, picking and transferring wafers. The carrier substrate can be a sapphire substrate, a quartz substrate or other substrates that can sustain further processing, such as thermal treatments and/or chemical etchings. The method of the present invention not only prevents possible damages to the highly brittle chip after wafer thinning, but also fits the conventional production line for processing semiconductor wafers.
摘要翻译：公开了一种将薄化的半导体晶片安装在用于进一步处理的载体基板上的方法。该方法包括一系列步骤，其基于提供具有双面胶带的框架以将减薄的晶片安装在载体基板上。该框架用于支撑双面胶带，并且可以设计成适合用于保持，拾取和转印晶片的常规生产线。载体衬底可以是蓝宝石衬底，石英衬底或可以承受进一步加工的其它衬底，例如热处理和/或化学蚀刻。本发明的方法不仅可以防止在晶片变薄之后对高脆性芯片造成可能的损坏，而且还适用于用于处理半导体晶片的常规生产线。

7. 发明申请

US20110059610A1 Method of using an electroless plating for depositing a metal seed layer for the subsequent plated backside metal film 有权
公开(公告)号：US20110059610A1
公开(公告)日：2011-03-10
申请号：US12656073
申请日：2010-01-15
申请人： Chang-Hwang Hua , Wen Chu
发明人： Chang-Hwang Hua , Wen Chu
IPC分类号： H01L21/3205
CPC分类号： H01L21/76898
摘要： A method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating for depositing a metal seed layer for the plated backside metal film. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by electroless plating. Then, the backside metal layer, such as a gold layer or a copper layer, is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the backside metal layer through backside via holes, but also prevents metal peeling after subsequent fabrication processes. This is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Cu, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes.

8. 发明授权

US08003532B2 Method of using an electroless plating for depositing a metal seed layer for the subsequent plated backside metal film 有权
标题翻译：使用化学镀以沉积后续镀覆的背面金属膜的金属种子层的方法
公开(公告)号：US08003532B2
公开(公告)日：2011-08-23
申请号：US12656073
申请日：2010-01-15
申请人： Chang-Hwang Hua , Wen Chu
发明人： Chang-Hwang Hua , Wen Chu
IPC分类号： H01L21/78 , H01L21/46 , H01L21/301 , H01L21/44
CPC分类号： H01L21/76898
摘要： A method of backside metal process for semiconductor electronic devices, particularly of using an electroless plating for depositing a metal seed layer for the plated backside metal film. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by electroless plating. Then, the backside metal layer, such as a gold layer or a copper layer, is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the backside metal layer through backside via holes, but also prevents metal peeling after subsequent fabrication processes. This is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Cu, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes.
摘要翻译：一种用于半导体电子器件的背面金属工艺的方法，特别是使用化学镀来沉积用于镀覆的背面金属膜的金属籽晶层。已经制造在前侧的电子器件的半导体晶片的背面首先通过化学镀被薄金属种子层涂覆。然后，将金属层或铜层等背面金属层涂覆在金属种子层上。金属种子层不仅通过背面通孔增加前侧金属层和背面金属层之间的粘附力，而且防止后续制造工艺中的金属剥离。这有助于提高设备性能的可靠性。用于金属种子层的合适的材料包括Pd，Au，Ni，Ag，Co，Cr，Cu，Pt或它们的合金，例如NiP，NiB，AuSn，Pt-Rh等。

9. 发明申请

US20100035405A1 Method for mounting a thinned semiconductor wafer on a carrier substrate 有权
标题翻译：将减薄的半导体晶片安装在载体基板上的方法
公开(公告)号：US20100035405A1
公开(公告)日：2010-02-11
申请号：US12222343
申请日：2008-08-07
申请人： Jason Chou , Chang-Hwang Hua , Ping-Wei Chen , Sen Yang
发明人： Jason Chou , Chang-Hwang Hua , Ping-Wei Chen , Sen Yang
IPC分类号： H01L21/762
CPC分类号： H01L21/187 , H01L31/0392 , H01L31/1896 , Y02E10/50 , Y10T29/49126 , Y10T29/4913
摘要： A method for mounting a thinned semiconductor wafer on a carrier substrate for further processing is disclosed. The method consists of a series of steps, which is based on providing a frame with a double-side tape to mount the thinned wafer on the carrier substrate. The frame is used to support the double-side tape and can be designed to fit the conventional production line for holding, picking and transferring wafers. The carrier substrate can be a sapphire substrate, a quartz substrate or other substrates that can sustain further processing, such as thermal treatments and/or chemical etchings. The method of the present invention not only prevents possible damages to the highly brittle chip after wafer thinning, but also fits the conventional production line for processing semiconductor wafers.
摘要翻译：公开了一种将薄化的半导体晶片安装在用于进一步处理的载体基板上的方法。该方法包括一系列步骤，其基于提供具有双面胶带的框架以将减薄的晶片安装在载体基板上。该框架用于支撑双面胶带，并且可以设计成适合用于保持，拾取和转印晶片的常规生产线。载体衬底可以是蓝宝石衬底，石英衬底或可以承受进一步加工的其它衬底，例如热处理和/或化学蚀刻。本发明的方法不仅可以防止在晶片变薄之后对高脆性芯片造成可能的损坏，而且还适用于用于处理半导体晶片的常规生产线。

10. 发明授权

US08911551B2 Electroless plating apparatus and method 有权
标题翻译：化学镀设备及方法
公开(公告)号：US08911551B2
公开(公告)日：2014-12-16
申请号：US13196179
申请日：2011-08-02
申请人： Jason Chen , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
发明人： Jason Chen , Nakano Liu , Winson Shao , Wen Chu , Chang-Hwang Hua
IPC分类号： B05C11/00 , C23C18/16 , H01L21/768 , H01L21/288
CPC分类号： H01L21/288 , C23C18/1619 , C23C18/1666 , C23C18/1669 , H01L21/76843
摘要： An electroless plating apparatus and method designed specifically for plating at least one semiconductor wafer are disclosed. The apparatus comprises a container, a wafer holder, an electrolyte supplying unit, and an ultrasonic-vibration unit. The container is provided with at least an inlet and used for containing electrolyte. The wafer holder is provided within the container. The electrolyte supplying unit is used to supply the electrolyte into the container via the inlet. The ultrasonic-vibration unit consisting of at least one frequency ultrasonic transducer is disposed in the container for producing a uniform flow of electrolyte in the container. Thereby, the wafers can be uniformly plated, especially for wafers with fine via-holes or trench structures.
摘要翻译：公开了专门用于电镀至少一个半导体晶片的化学镀设备和方法。该装置包括容器，晶片保持器，电解质供给单元和超声波振动单元。容器设有至少一个入口并用于容纳电解质。晶片保持器设置在容器内。电解质供给单元用于经由入口将电解质供给到容器中。由至少一个频率超声波换能器组成的超声波振动单元设置在容器中，用于在容器中产生均匀的电解液流。因此，可以均匀地镀覆晶片，特别是对于具有精细通孔或沟槽结构的晶片。

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