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31. 发明授权

US06563758B2 Multiple ports memory-cell structure 失效
公开(公告)号：US06563758B2
公开(公告)日：2003-05-13
申请号：US10066262
申请日：2002-01-31
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C800
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/12 , G11C7/18 , G11C8/12 , G11C11/406 , G11C11/4074 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , H01L27/10829 , H01L27/10897
摘要： A semiconductor memory array comprises a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage. In a preferred embodiment, the memory cell read/write voltage control circuit further includes a wordline voltage control circuit for providing a higher wordline voltage in a write operation and a lower wordline voltage in a read operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core power supply voltage (CVdd) control circuit for providing a higher CVdd voltage in a read operation and a lower CVdd voltage in a write operation. In another preferred embodiment, the memory cell read/write voltage control circuit further includes a memory-core ground voltage (CVss) control circuit for providing a lower CVss voltage in a read operation and a higher CVss voltage in a write operation.

32. 发明授权

US06504745B2 High performance erasable programmable read-only memory (EPROM) devices with multiple dimension first-level bit lines 失效
公开(公告)号：US06504745B2
公开(公告)日：2003-01-07
申请号：US09860215
申请日：2001-05-18
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C506
CPC分类号： G11C7/1006 , G11C7/18 , G11C8/12 , G11C11/406 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L27/10829 , H01L27/10897
摘要： A semiconductor erasable programmable read-only memory (EPROM) device provided for operation with a plurality of first level sense-circuits. The EPROM memory device includes an EPROM memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction. The EPROM memory device further includes a plurality of word lines intersected with the first-direction first-level bit lines. The EPROM memory cell array further includes a plurality of EPROM memory cells wherein each of the plurality of memory cells being coupled between one of the first-direction first level bit lines and one of the word lines for storing data therein. And, the EPROM memory device further includes a plurality of different-direction first level bit-lines disposed along at least one different direction different from the first direction. Each of the different-direction first-level bit lines connected between a plurality of the first-direction first level bit lines and one of the first level sense-circuits.

33. 发明授权

US06492835B2 Power saving methods for programmable logic arrays 失效
标题翻译：可编程逻辑阵列的省电方法
公开(公告)号：US06492835B2
公开(公告)日：2002-12-10
申请号：US09966141
申请日：2001-09-28
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H03K19177
CPC分类号： G06F7/02 , G06F7/24 , G06F17/5054 , H03K19/177 , H03K19/17708 , H03K19/17736 , H03K19/17784
摘要： The present invention provides novel power saving methods for programmable logic array (PLA) circuits. One method is to store the results of a previous PLA operation, and bypass a new operation if the inputs are the same as previous operation. Another method is to reset the PLA outputs when the correct results can be achieved by resetting output latches. A large PLA is divided into smaller sub-PLA's while individual sub-PLA's are controlled separately. It is therefore possible to save power by bypassing unrelated sub-PLA's. PLA's of the present invention consume less power than equivalent prior art PLA's by orders of magnitudes. For most cases, PLA's of the present invention also have better performance and better cost efficiency. The design procedures are completely controlled by user-friendly computer aid design tools. The regular structures of PLA and the simplicity in connections allow us to avoid RC effects of conductor lines. We are able to achieve full performance improvement as IC technologies continue to progress into smaller and smaller critical dimensions.
摘要翻译：本发明为可编程逻辑阵列（PLA）电路提供了新颖的省电方法。一种方法是存储先前PLA操作的结果，如果输入与前一操作相同，则绕过新操作。另一种方法是在通过复位输出锁存器来实现正确的结果时复位PLA输出。大型解放军分为小型解放军，个别解放军单独控制。因此可以通过绕过无关的分PLA来节省电力。本发明的解放军的兵力比现有技术人员的兵力要低很多。在大多数情况下，本发明的PLA也具有更好的性能和更好的成本效率。设计程序由用户友好的计算机辅助设计工具完全控制。 PLA的正常结构和连接的简单性使我们能够避免导线的RC效应。我们能够实现全面的性能改进，因为IC技术将继续发展成越来越小的关键维度。

34. 发明授权

US09666055B2 Distress signal transmitters 有权
公开(公告)号：US09666055B2
公开(公告)日：2017-05-30
申请号：US14840027
申请日：2015-08-30
申请人： David Yen Shau , Jeng-Jye Shau
发明人： David Yen Shau , Jeng-Jye Shau
IPC分类号： G08B23/00 , G08B21/08
CPC分类号： G08B21/088 , G01S5/0231
摘要： Distress signal transmitters of the present invention are designed to maximize the chance for a victim to survive an accident, and minimize the time for a rescue party to find a victim. The preferred embodiments of the distress signal transmitters of the present invention are to be self-powered, self-activated, and to remain fully functional when dropped into salt water. This will allow the Radio Frequency (RF) distress signals to be sent over a long distance, even if the user is unconscious or severely injured. Furthermore, a set of coordinates determined by a Global Positioning System will be transmitted with the S.O.S message in order for search parties to quickly and efficiently pinpoint the location of the victim(s).

35. 发明授权

US09536690B2 High performance power input circuits using synchronized mechanical switches 有权
标题翻译：使用同步机械开关的高性能电源输入电路
公开(公告)号：US09536690B2
公开(公告)日：2017-01-03
申请号：US14070375
申请日：2013-11-01
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H01H45/00 , H02M1/24 , H02M7/32 , H01H1/40 , H01H50/54 , H01H50/64 , H01H3/40
CPC分类号： H01H45/00 , H01H1/403 , H01H3/40 , H01H50/54 , H01H50/64 , H02M1/24 , H02M7/32 , Y10T307/76
摘要： Synchronized mechanical switches are configured to support electrical switching circuits operating at frequencies equal to or higher than the frequency of the primary AC power supply. Due to near perfect impedances of mechanical switches as well as accurate timing control mechanisms, the mechanical switching circuits provide timely electrical connections to the terminals of the primary AC power supply to generate proper waveforms suitable to power next stage electrical circuits without the need to use semiconductor devices.
摘要翻译：同步机械开关被配置为支持以等于或高于主交流电源的频率的频率工作的电气开关电路。由于机械开关的接近完美的阻抗以及精确的定时控制机构，机械开关电路提供及时的电连接到主交流电源的端子，以产生适合于为下一级电路供电的适当波形，而无需使用半导体设备。

36. 发明申请

US20160241062A1 ELECTRICAL POWER CONVERTER CIRCUITS 审中-公开
标题翻译：电力转换器电路
公开(公告)号：US20160241062A1
公开(公告)日：2016-08-18
申请号：US14621364
申请日：2015-02-12
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H02J7/00 , H02M7/04
CPC分类号： H02M7/04 , H02J7/0052 , H02J7/0093 , H02J7/022 , H02J2007/0059 , H02M3/07
摘要： The preferred embodiments of the present invention changes the switch control mechanisms of switched-mode power converter circuits. Instead of controlling the duty cycle of switch control signals, the preferred embodiments of the present invention controls electrical switches based on the voltage level on the fire line of AC main power source. The resulting power converter circuits operates at better power efficiency while achieving significantly better space/cost efficiency, and they are small enough while powerful enough to be embedded into battery powered mobile devices.
摘要翻译：本发明的优选实施例改变了开关式功率转换器电路的开关控制机制。代替控制开关控制信号的占空比，本发明的优选实施例基于AC主电源的火线上的电压电平来控制电开关。所得到的功率转换器电路以更好的功率效率工作，同时实现显着更好的空间/成本效率，并且它们足够小，而足够强大以便嵌入到电池供电的移动设备中。

37. 发明申请

US20140240028A1 HIGH VOLTAGE SWITCHING CIRCUITS 审中-公开
标题翻译：高电压开关电路
公开(公告)号：US20140240028A1
公开(公告)日：2014-08-28
申请号：US13779761
申请日：2013-02-28
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H03K17/687
CPC分类号： H03K17/6874 , H02M2001/0074 , H03K17/102 , H03K17/691
摘要： The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits. The resulting circuits can support high voltage applications while achieving cost and performance advantages of low voltage circuits.
摘要翻译：本发明的优选实施例使用低压晶体管来通过连接堆叠配置中的低电压电路来支持高压开关电路。在将高压开关信号发送到变压器，滤波器或其他电路之前，将高压开关信号分为多个小幅度切换信号。所得到的电路可以支持高电压应用，同时实现低压电路的成本和性能优点。

38. 发明申请

US20110089555A1 AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS 有权
标题翻译：面积安装套件面积减少
公开(公告)号：US20110089555A1
公开(公告)日：2011-04-21
申请号：US12686551
申请日：2010-01-13
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H01L23/48 , H01L23/12 , H01L21/60
CPC分类号： H01L23/48 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/072 , H01L27/0255 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/49171 , H01L2225/06551 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/09701 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , Y10T29/49121 , Y10T29/49147 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
摘要翻译：使用由侧壁绝缘体绝缘的侧壁导体引线形成用于在硅衬底上制造的有源电路的封装级导体引线，本发明的优选实施例显着地减少了表面贴装封装芯片的面积。除了减少面积之外，这些方法还显着降低了成本并降低了寄生阻抗。

39. 发明申请

US20100237904A1 High Performance Output Drivers and Anti-Reflection Circuits 审中-公开
标题翻译：高性能输出驱动器和反反射电路
公开(公告)号：US20100237904A1
公开(公告)日：2010-09-23
申请号：US12795005
申请日：2010-06-07
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H03K19/003 , H03K3/00
CPC分类号： H03K19/018585 , H04L25/0264 , H04L25/0272 , H04L25/028
摘要： Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).
摘要翻译：通过使用n沟道晶体管作为上拉晶体管和/或p沟道晶体管作为高性能输出驱动器的下拉晶体管来解决已知输出驱动器的长期存在的性能，噪声和功耗问题。片上终端电路分支为连接到同一传输线的多个芯片提供有效的防反射功能。

40. 发明申请

US20090103373A1 HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS 审中-公开
公开(公告)号：US20090103373A1
公开(公告)日：2009-04-23
申请号：US12039680
申请日：2008-02-28
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C7/10
CPC分类号： G11C11/4093 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications.

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