专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20220146860A1 ERGONOMIC PROTECTIVE EYEWEAR 有权
公开(公告)号：US20220146860A1
公开(公告)日：2022-05-12
申请号：US17582468
申请日：2022-01-24
申请人： Alexander Yen Shau , Jeng-Jye Shau
发明人： Alexander Yen Shau , Jeng-Jye Shau
IPC分类号： G02C7/14 , G02B25/00
摘要： Using a camera pointing downward, a working area below eye level can be displayed by a headwear for users, so that the user can maintain healthy sitting or standing posture while working on patients or objects located below eye level. Using two or more cameras pointing downward, three-dimensional views with accurate and natural depth perception of a working area can be displayed by a headwear for users. Additional functions including eye protection, zoom-in, zoom-out, on-off, lighting control, overlapping, and teleconference capabilities are also supported using electronic, video and audio devices associated with the headwear. The headwear can also comprise a face shield designed to protect the user from hazardous droplets, aerosols, harmful wavelengths of light, heat, sparks, flash burn, debris and/or flying objects. Contactless control devices can be used to control the functions of the headwear.

2. 发明授权

US11272170B2 Ergonomic protective eyewear 有权
公开(公告)号：US11272170B2
公开(公告)日：2022-03-08
申请号：US16915972
申请日：2020-06-29
申请人： Alexander Shau , Jeng-Jye Shau
发明人： Alexander Shau , Jeng-Jye Shau
IPC分类号： H04N13/344 , A61B90/00 , A61B90/53 , A61F9/02 , H04N13/239 , A61B1/247 , A41D13/11 , A61B90/50
摘要： Using two or more cameras attached to the eyewear, three-dimensional views with accurate and natural depth perception of the working area can be displayed for users, so that the user can maintain healthy sitting or standing posture while working on patients or objects located below horizontal eye level. Additional functions including eye protection, zoom-in, zoom-out, on-off, lighting control, overlapping, and teleconference capabilities are also supported using electronic, video and audio devices attached to the eyewear. The eyewear can also comprise a face shield designed to protect the user from hazardous droplets, aerosols, harmful wavelengths of light, heat, sparks, flash burn, debris and/or flying objects.

3. 发明申请

US20170069195A1 DISTRESS SIGNAL TRANSMITTERS 审中-公开
标题翻译： DISTRESS信号发射器
公开(公告)号：US20170069195A1
公开(公告)日：2017-03-09
申请号：US14840027
申请日：2015-08-30
申请人： David Yen Shau , Jeng-Jye Shau
发明人： David Yen Shau , Jeng-Jye Shau
IPC分类号： G08B21/08
CPC分类号： G08B21/088 , G01S5/0231
摘要： Distress signal transmitters of the present invention are designed to maximize the chance for a victim to survive an accident, and minimize the time for a rescue party to find a victim. The preferred embodiments of the distress signal transmitters of the present invention are to be self-powered, self-activated, and to remain fully functional when dropped into salt water. This will allow the Radio Frequency (RF) distress signals to be sent over a long distance, even if the user is unconscious or severely injured. Furthermore, a set of coordinates determined by a Global Positioning System will be transmitted with the S.O.S message in order for search parties to quickly and efficiently pinpoint the location of the victim(s).
摘要翻译：本发明的遇险信号发射器被设计成使得受害者在事故中生存的机会最大化，并且使救援人员找到受害者的时间最小化。本发明的遇险信号发射机的优选实施例将是自供电的，自激活的，并且在落入盐水时保持完全功能。即使使用者无意识或严重受伤，这样也可以使射频（RF）遇险信号长距离发送。此外，由全球定位系统确定的一组坐标将与S.O.S消息一起发送，以便搜索方快速有效地确定受害者的位置。

4. 发明申请

US20150123493A1 HIGH PERFORMANCE POWER INPUT CIRCUITS USING SYNCHRONIZED MECHANICAL SWITECHES 审中-公开
标题翻译：使用同步机械式开关的高性能功率输入电路
公开(公告)号：US20150123493A1
公开(公告)日：2015-05-07
申请号：US14070375
申请日：2013-11-01
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H02M1/20 , H01H45/00
CPC分类号： H01H45/00 , H01H1/403 , H01H3/40 , H01H50/54 , H01H50/64 , H02M1/24 , H02M7/32 , Y10T307/76
摘要： The preferred embodiments of the present invention use synchronized mechanical switches to support electrical switching circuits. Due to near perfect impedances of mechanical switches as well as accurate timing control mechanisms, the preferred embodiments of the present invention provide significant improvements in power efficiency and cost efficiency of first stage power input circuits.
摘要翻译：本发明的优选实施例使用同步机械开关来支持电开关电路。由于机械开关接近完美的阻抗以及精确的定时控制机构，本发明的优选实施例提供了第一级电力输入电路的功率效率和成本效率方面的显着改进。

5. 发明申请

US20110133773A1 High Performance Output Drivers and Anti-Reflection Circuits 审中-公开
标题翻译：高性能输出驱动器和反反射电路
公开(公告)号：US20110133773A1
公开(公告)日：2011-06-09
申请号：US12772143
申请日：2010-04-30
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/0005 , H03K19/01721 , H03K19/0941 , H04L25/0278
摘要： Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).
摘要翻译：通过使用n沟道晶体管作为上拉晶体管和/或p沟道晶体管作为高性能输出驱动器的下拉晶体管来解决已知输出驱动器的长期存在的性能，噪声和功耗问题。片上终端电路分支为连接到同一传输线的多个芯片提供有效的防反射功能。

6. 发明申请

US20110089557A1 Area reduction for die-scale surface mount package chips 审中-公开
标题翻译：用于模具尺寸表面贴装封装芯片的面积缩小
公开(公告)号：US20110089557A1
公开(公告)日：2011-04-21
申请号：US12636474
申请日：2009-12-11
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H01L23/52 , H01L21/60
CPC分类号： H01L23/3114 , H01L21/561 , H01L21/568 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/072 , H01L27/0255 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/49171 , H01L2225/06551 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/09701 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Using side-wall conductor leads to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of die-scale surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
摘要翻译：使用侧壁导体引线形成用于在硅衬底上制造的有源电路的封装级导体引线，本发明的优选实施例显着地减少了裸片刻度表面贴装封装芯片的面积。除了减少面积之外，这些方法还显着降低了成本并降低了寄生阻抗。

7. 发明授权

US07064971B2 Methods for saving power and area for content addressable memory devices 失效
公开(公告)号：US07064971B2
公开(公告)日：2006-06-20
申请号：US10752317
申请日：2004-01-05
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost saving for high density CAM products. The power consumption problems of prior art high density CAM devices are solved by novel zoned lookup mechanism. For a high density CAM storing sorted data, lookup mechanisms of the present invention can reduce power consumption by two orders of magnitudes.

8. 发明申请

US20050201025A1 Capacitor coupling circuits 审中-公开
标题翻译：电容耦合电路
公开(公告)号：US20050201025A1
公开(公告)日：2005-09-15
申请号：US10796318
申请日：2004-03-09
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： H02H7/00
CPC分类号： H01L29/94 , H01L27/0629 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/118 , H01L28/60 , H01L29/788 , H03K19/018521 , H03K19/0941
摘要： The present invention utilizes voltage coupling effects of MOS capacitors to support logic operations for integrated circuits such as programmable logic array, optical sensors, comparators, and storage devices. Additional flexibility is achieved by using the voltage coupling effects of floating gate capacitors to support applications such as field programmable logic and non-volatile memory devices. Integrated circuits of the present invention occupy much smaller areas comparing to equivalent prior art integrated circuits, achieving dramatic cost reduction. Further cost reduction can be achieved by fabricating coupling circuits of the present invention on low quality substrates as 3 dimensional devices. The major drawback of the present invention is smaller signal to noise ratio, which is overcome by proper voltage control and sensing circuits. Special considerations to support hot carrier programming and current mode reading are also disclosed in this patent.
摘要翻译：本发明利用MOS电容器的电压耦合效应来支持诸如可编程逻辑阵列，光学传感器，比较器和存储装置之类的集成电路的逻辑运算。通过使用浮动栅极电容器的电压耦合效应来支持诸如现场可编程逻辑和非易失性存储器件的应用来实现额外的灵活性。与现有技术的集成电路相比，本发明的集成电路占据了更小的面积，从而实现了显着的成本降低。通过将本发明的耦合电路制成低质量的基板作为3维器件，可以进一步降低成本。本发明的主要缺陷是较小的信噪比，这被适当的电压控制和感测电路所克服。本专利还公开了支持热载波编程和当前模式读取的特殊考虑。

9. 发明申请

US20050169090A1 Method for making high performance semiconductor memory devices 审中-公开
标题翻译：制造高性能半导体存储器件的方法
公开(公告)号：US20050169090A1
公开(公告)日：2005-08-04
申请号：US11006256
申请日：2004-12-07
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C7/06 , G11C8/12 , G11C8/00
CPC分类号： G11C8/12 , G11C7/06
摘要： High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.
摘要翻译：已经通过使用块选择布置应用均匀扩展多级架构（ESMLA）来实现高性能存储器件。单位线写机制允许我们将静态存储器件的位线数减少50％。所得到的存储器件可以与寄存器文件一样快，而其面积小于现有技术的高密度存储器件。存储器架构的缩放方法还确保了存储器件的速度在未来的IC制造技术中将以与逻辑电路相同的速率缩放。

10. 发明授权

US06829180B2 High performance semiconductor memory devices 失效
标题翻译：高性能半导体存储器件
公开(公告)号：US06829180B2
公开(公告)日：2004-12-07
申请号：US10442016
申请日：2003-05-19
申请人： Jeng-Jye Shau
发明人： Jeng-Jye Shau
IPC分类号： G11C1604
CPC分类号： G11C8/12 , G11C7/06
摘要： High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.
摘要翻译：已经通过使用块选择布置应用均匀扩展多级架构（ESMLA）来实现高性能存储器件。单位线写机制允许我们将静态存储器件的位线数减少50％。所得到的存储器件可以与寄存器文件一样快，而其面积小于现有技术的高密度存储器件。存储器架构的缩放方法还确保了存储器件的速度在未来的IC制造技术中将以与逻辑电路相同的速率缩放。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式