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31. 发明申请

US20090163008A1 Lithographically Space-Defined Charge Storage Regions In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的光刻空间定义电荷存储区域
公开(公告)号：US20090163008A1
公开(公告)日：2009-06-25
申请号：US11960513
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/28
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译：在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域的第一电荷存储区域。

32. 发明申请

US20090162951A1 Enhanced Endpoint Detection In Non-Volatile Memory Fabrication Processes 有权
标题翻译：在非易失性存储器制造过程中增强端点检测
公开(公告)号：US20090162951A1
公开(公告)日：2009-06-25
申请号：US11960485
申请日：2007-12-19
申请人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
发明人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L27/11521
摘要： A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
摘要翻译：提供一种制造非易失性存储器的方法，用于采用具有多个电荷存储区域的电荷存储元件的存储单元。第一电荷存储层在半导体衬底的存储器阵列区域和端点区域的隧道电介质层上形成。从端点区域去除第一电荷存储层以暴露隧道电介质区域。第二电荷存储层形成在存储器阵列区域的第一电荷存储层上，并在端点区域的隧道电介质层上形成。当蚀刻第二电荷存储层以形成存储器单元的干区域时，隧道介电层提供可检测的端点信号，以指示第二电荷存储层的蚀刻完成。

33. 发明授权

US07494870B2 Methods of forming NAND memory with virtual channel 有权
标题翻译：用虚拟通道形成NAND存储器的方法
公开(公告)号：US07494870B2
公开(公告)日：2009-02-24
申请号：US11626784
申请日：2007-01-24
申请人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
发明人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

34. 发明授权

US08222091B2 Damascene method of making a nonvolatile memory device 有权
标题翻译：制作非易失性存储器件的镶嵌方法
公开(公告)号：US08222091B2
公开(公告)日：2012-07-17
申请号：US13309857
申请日：2011-12-02
申请人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
发明人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.
摘要翻译：一种制造器件的方法包括提供包含由第一绝缘特征分开的第一半导体轨道的第一器件电平，在第一器件电平上形成牺牲层，在第一器件电平图形化牺牲层和第一半导体轨道以形成多个的第二轨道，其沿着第二方向延伸，其中所述多个第二轨道至少部分地延伸到所述第一装置水平面并且通过至少部分地延伸到所述第一装置水平的轨道形开口彼此分开，所述多个第二轨道，去除所述牺牲层，以及在所述第二设备水平上的第二设备水平的所述第二绝缘特征之间形成第二半导体轨道。第一半导体轨道沿第一方向延伸。第二半导体轨道沿与第一方向不同的第二方向延伸。

35. 发明授权

US08143156B2 Methods of forming high density semiconductor devices using recursive spacer technique 有权
标题翻译：使用递归间隔技术形成高密度半导体器件的方法
公开(公告)号：US08143156B2
公开(公告)日：2012-03-27
申请号：US11765866
申请日：2007-06-20
申请人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
发明人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.
摘要翻译：公开了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。可以处理第一组间隔件以提供平面和平行的侧壁。可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

36. 发明授权

US07888210B2 Non-volatile memory fabrication and isolation for composite charge storage structures 有权
标题翻译：用于复合电荷存储结构的非易失性存储器制造和隔离
公开(公告)号：US07888210B2
公开(公告)日：2011-02-15
申请号：US11960518
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译：制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。

37. 发明授权

US07732275B2 Methods of forming NAND flash memory with fixed charge 有权
标题翻译：用固定电荷形成NAND闪存的方法
公开(公告)号：US07732275B2
公开(公告)日：2010-06-08
申请号：US11692961
申请日：2007-03-29
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

38. 发明申请

US20090261398A1 NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 有权
标题翻译：非易失性存储器，带有通道和扩展源/漏区
公开(公告)号：US20090261398A1
公开(公告)日：2009-10-22
申请号：US12105242
申请日：2008-04-17
申请人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
发明人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
IPC分类号： H01L29/788
CPC分类号： G11C8/10 , G11C8/04 , G11C11/5621 , G11C16/0483 , G11C19/00 , H01L21/28273 , H01L27/11521
摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.
摘要翻译：一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。浮动门可以具有均匀的宽度或倒T形。凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为减少侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

39. 发明申请

US20090162977A1 Non-Volatile Memory Fabrication And Isolation For Composite Charge Storage Structures 有权
标题翻译：用于复合电荷存储结构的非易失性存储器制造和隔离
公开(公告)号：US20090162977A1
公开(公告)日：2009-06-25
申请号：US11960518
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Fabricating semiconductor-based non-volatile memory that includes composite storage elements, such as those with first and second charge storage regions, can include etching more than one charge storage layer. To avoid inadvertent shorts between adjacent storage elements, a first charge storage layer for a plurality of non-volatile storage elements is formed into rows prior to depositing the second charge storage layer. Sacrificial features can be formed between the rows of the first charge storage layer that are adjacent in a column direction, before or after forming the rows of the first charge layer. After forming interleaving rows of the sacrificial features and the first charge storage layer, the second charge storage layer can be formed. The layers can then be etched into columns and the substrate etched to form isolation trenches between adjacent columns. The second charge storage layer can then be etched to form the second charge storage regions for the storage elements.
摘要翻译：制造包括诸如具有第一和第二电荷存储区域的那些的复合存储元件的基于半导体的非易失性存储器可以包括蚀刻多于一个电荷存储层。为了避免相邻存储元件之间的意外短路，在沉积第二电荷存储层之前，用于多个非易失性存储元件的第一电荷存储层形成为行。可以在形成第一电荷层的行之前或之后，在列方向上相邻的第一电荷存储层的行之间形成牺牲特征。在形成牺牲特征和第一电荷存储层的交错行之后，可以形成第二电荷存储层。然后可以将这些层蚀刻成柱，并且蚀刻衬底以在相邻柱之间形成隔离沟槽。然后可以蚀刻第二电荷存储层以形成用于存储元件的第二电荷存储区域。

40. 发明申请

US20090155967A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权
标题翻译：使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
公开(公告)号：US20090155967A1
公开(公告)日：2009-06-18
申请号：US11958941
申请日：2007-12-18
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

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