专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08153493B2 FinFET process compatible native transistor 有权
标题翻译： FinFET工艺兼容天然晶体管
公开(公告)号：US08153493B2
公开(公告)日：2012-04-10
申请号：US12267121
申请日：2008-11-07
申请人： Jam-Wem Lee
发明人： Jam-Wem Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/6659 , H01L29/7834 , H01L29/785
摘要： Provided is a top-channel only finFET device. The methods and devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate.
摘要翻译：提供了仅顶部通道finFET器件。本文所述的方法和装置可以提供与finFET工艺流程兼容的本机器件。可以在提供器件的沟道区域的翅片的顶部上形成栅极。在一个实施例中，门仅设置在通道的一侧上，例如在翅片的顶部。包括通道的翅片的侧壁可以邻接隔离结构。在一个实施例中，在翅片之间形成隔离结构以提供用于形成栅极的平面。

32. 发明申请

US20090315112A1 Forming ESD Diodes and BJTs Using FinFET Compatible Processes 有权
标题翻译：使用FinFET兼容工艺形成ESD二极管和BJT
公开(公告)号：US20090315112A1
公开(公告)日：2009-12-24
申请号：US12143644
申请日：2008-06-20
申请人： Jam-Wem Lee
发明人： Jam-Wem Lee
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L21/823431 , H01L27/0248 , H01L29/66795 , H01L29/785
摘要： A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT.
摘要翻译：形成静电放电（ESD）器件的方法包括在衬底上形成彼此相邻的第一和第二半导体鳍; 在所述第一半导体鳍片和所述第二半导体鳍片上外延生长半导体材料，其中从所述第一半导体鳍片生长的所述半导体材料的第一部分接合从所述第二半导体鳍片生长的所述半导体材料的第二部分; 以及植入半导体材料的第一端和第二端以及第一和第二半导体鳍片的第一端部分别分别形成第一和第二植入区域。在半导体材料的第一端和第二端之间形成P-N结。 P-N结是ESD二极管或NPN或PNP BJT中的结的结。

33. 发明授权

US08963200B2 Methods and apparatus for increased holding voltage in silicon controlled rectifiers for ESD protection 有权
标题翻译：用于ESD保护的可控硅整流器中增加保持电压的方法和装置
公开(公告)号：US08963200B2
公开(公告)日：2015-02-24
申请号：US13527833
申请日：2012-06-20
申请人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
发明人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
IPC分类号： H01L29/45
CPC分类号： H01L27/0262 , H01L21/8248 , H01L23/60 , H01L23/62 , H01L27/0921 , H01L29/0619 , H01L29/73 , H01L29/812
摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.
摘要翻译：提高保持电压SCR的方法和装置。半导体器件包括第一导电类型的半导体衬底; 第一导电类型的第一井; 与第一阱相邻的第二导电类型的第二阱，形成p-n结的第一阱和第二阱的交点; 第一导电类型的第一扩散区域形成在第一阱处并且耦合到接地端子; 形成在第一阱处的第二导电类型的第一扩散区域; 第二导电类型的第二扩散区域形成在第二阱处并耦合到焊盘端子; 第二导电类型的第二扩散区形成在第二阱中; 以及与第二导电类型的第一扩散区相邻形成的与肖特基结相连的接地端子。公开了用于形成装置的方法。

34. 发明授权

US08742491B2 FinFET process compatible native transistor 有权
标题翻译： FinFET工艺兼容天然晶体管
公开(公告)号：US08742491B2
公开(公告)日：2014-06-03
申请号：US13362811
申请日：2012-01-31
申请人： Jam-Wem Lee
发明人： Jam-Wem Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/66628 , H01L29/6659 , H01L29/7834 , H01L29/785
摘要： Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate.
摘要翻译：提供了仅顶部通道finFET器件。本文所述的装置可以提供与finFET工艺流程兼容的本机装置。可以在提供器件的沟道区域的翅片的顶部上形成栅极。在一个实施例中，门仅设置在通道的一侧上，例如在翅片的顶部。包括通道的翅片的侧壁可以邻接隔离结构。在一个实施例中，在翅片之间形成隔离结构以提供用于形成栅极的平面。

35. 发明申请

US20140062580A1 Diode Formed of PMOSFET and Schottky Diodes 有权
标题翻译： PMOSFET和肖特基二极管形成的二极管
公开(公告)号：US20140062580A1
公开(公告)日：2014-03-06
申请号：US13604299
申请日：2012-09-05
申请人： Jam-Wem Lee , Wan-Yen Lin , Ming-Hsiang Song , Cheng-Hsiung Kuo , Yue-Der Chih
发明人： Jam-Wem Lee , Wan-Yen Lin , Ming-Hsiang Song , Cheng-Hsiung Kuo , Yue-Der Chih
IPC分类号： G05F3/02
CPC分类号： H01L27/0727 , H01L27/0222 , H01L29/0619 , H01L29/872 , H02M3/07
摘要： A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.
摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）包括栅极，连接到栅极的第一源极/漏极区域和栅极相对于第一源极/漏极的第二源极/漏极区域地区。第一肖特基二极管包括连接到第一源极/漏极区域的第一阳极和连接到PMOSFET主体的第一阴极。第二肖特基二极管包括连接到第二源极/漏极区的第二阳极和连接到PMOSFET的主体的第二阴极。

36. 发明申请

US20140061848A1 Schottky Isolated NMOS for Latch-Up Prevention 有权
标题翻译：肖特基隔离NMOS用于锁存预防
公开(公告)号：US20140061848A1
公开(公告)日：2014-03-06
申请号：US13603329
申请日：2012-09-04
申请人： Yi-Feng Chang , Jam-Wem Lee
发明人： Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L29/06 , H01L21/329
CPC分类号： H01L27/0921 , H01L21/823892 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.
摘要翻译：集成电路结构包括衬底，由衬底支撑的半导体器件以及围绕半导体器件设置的保护环结构，保护环结构形成肖特基结。在一个实施例中，肖特基结由p型金属接触和n型保护环形成。在一个实施例中，保护环结构电耦合到正或负电源电压。

37. 发明申请

US20130341676A1 Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection 有权
公开(公告)号：US20130341676A1
公开(公告)日：2013-12-26
申请号：US13527833
申请日：2012-06-20
申请人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
发明人： Jam-Wem Lee , Tzu-Heng Chang , Tsung-Che Tsai , Ming-Hsiang Song
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L27/0262 , H01L21/8248 , H01L23/60 , H01L23/62 , H01L27/0921 , H01L29/0619 , H01L29/73 , H01L29/812
摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

38. 发明申请

US20130307080A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS 有权
标题翻译：具有自对准互连的半导体器件
公开(公告)号：US20130307080A1
公开(公告)日：2013-11-21
申请号：US13472890
申请日：2012-05-16
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
IPC分类号： H01L27/088 , H01L21/04
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括金属氧化物器件的衬底。金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。第一和第二掺杂区掺杂有第一类掺杂剂。第一掺杂区具有与第二掺杂区不同的掺杂浓度。金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。源区和漏区掺杂有第二类掺杂剂。第二种掺杂剂与第一种掺杂剂相反。

39. 发明授权

US08541848B2 High-voltage MOSFETs having current diversion region in substrate near fieldplate 有权
标题翻译：在场板附近的基板中具有电流分流区的高压MOSFET
公开(公告)号：US08541848B2
公开(公告)日：2013-09-24
申请号：US13271342
申请日：2011-10-12
申请人： Yun-Pei Huang , Yi-Feng Chang , Jam-Wem Lee
发明人： Yun-Pei Huang , Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/0653 , H01L29/063 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/7816
摘要： To limit or prevent current crowding, various HV-MOSFET embodiments include a current diversion region disposed near a drain region of an HV-MOSFET and near an upper surface of the semiconductor substrate. In some embodiments, the current diversion region is disposed near a field plate of the HV-MOSFET, wherein the field plate can also help to reduce or “smooth” electric fields near the drain to help limit current crowding. In some embodiments, the current diversion region is a p-doped, n-doped, or intrinsic region that is at a floating voltage potential. This current diversion region can push current deeper into the substrate of the HV-MOSFET (relative to conventional HV-MOSFETs), thereby reducing current crowding during ESD events. By reducing current crowding, the current diversion region makes the HV-MOSFETs disclosed herein more impervious to ESD events and, therefore, more reliable in real-world applications.
摘要翻译：为了限制或防止电流拥挤，各种HV-MOSFET实施例包括设置在HV-MOSFET的漏极区附近并且在半导体衬底的上表面附近的电流分流区域。在一些实施例中，电流引流区域设置在HV-MOSFET的场板附近，其中场板还可以帮助减少或“平滑”漏极附近的电场，以帮助限制电流拥挤。在一些实施例中，电流分流区域是处于浮置电压电位的p掺杂，n掺杂或本征区域。该电流分流区可以将电流深度推入HV-MOSFET的衬底（相对于传统HV-MOSFET），从而减少ESD事件期间的电流拥挤。通过减少电流拥挤，电流分流区域使得本文公开的HV-MOSFET更加不可避免地存在ESD事件，因此在现实世界的应用中更可靠。

40. 发明申请

US20130075854A1 High Voltage ESD Protection Apparatus 有权
标题翻译：高压ESD保护装置
公开(公告)号：US20130075854A1
公开(公告)日：2013-03-28
申请号：US13243688
申请日：2011-09-23
申请人： Yi-Feng Chang , Jam-Wem Lee
发明人： Yi-Feng Chang , Jam-Wem Lee
IPC分类号： H01L27/06
CPC分类号： H01L27/0259 , H01L23/50 , H01L27/0255 , H01L27/067 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/7302
摘要： An ESD protection apparatus comprises a metal contact formed on the emitter of a transistor. The metal contact has a different conductivity type from the emitter. In addition, the metal contact and the emitter of the transistor form a diode connected in series with the transistor. The diode connected in series with the transistor provides extra headroom for the breakdown voltage of the ESD protection apparatus.
摘要翻译： ESD保护装置包括形成在晶体管的发射极上的金属触点。金属触点具有与发射极不同的导电类型。此外，晶体管的金属接触和发射极形成与晶体管串联连接的二极管。与晶体管串联连接的二极管为ESD保护装置的击穿电压提供了额外的余量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式