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31. 发明授权

US08896123B2 Nonvolatile memory devices having a three dimensional structure 有权
标题翻译：具有三维结构的非易失性存储器件
公开(公告)号：US08896123B2
公开(公告)日：2014-11-25
申请号：US13478482
申请日：2012-05-23
申请人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
发明人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
IPC分类号： H01L27/115 , H01L23/522 , H01L29/792 , H01L29/94
CPC分类号： H01L27/11578 , H01L27/115 , H01L27/11517 , H01L27/11565 , H01L27/11582
摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
摘要翻译：具有三维结构的非易失性存储装置。非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

32. 发明申请

US20130171806A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20130171806A1
公开(公告)日：2013-07-04
申请号：US13779334
申请日：2013-02-27
申请人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
发明人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
IPC分类号： H01L21/02
CPC分类号： H01L21/02365 , H01L21/02697 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.
摘要翻译：提供一种三维半导体存储器件。三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

33. 发明授权

US08278170B2 Methods of forming nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein 有权
标题翻译：形成其中具有垂直集成的非易失性存储单元子串的非易失性存储器件的方法
公开(公告)号：US08278170B2
公开(公告)日：2012-10-02
申请号：US13165576
申请日：2011-06-21
申请人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
发明人： Changhyun Lee , Sunil Shim , Jaehoon Jang , Sunghoi Hur , Hansoo Kim , Kihyun Kim
IPC分类号： H01L21/336
CPC分类号： G11C16/28 , G11C16/14 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.
摘要翻译：形成根据本发明的实施例的非易失性存储器件的方法包括形成非易失性存储器单元的高度集成的垂直堆叠的技术。这些垂直堆叠的存储器单元可以利用虚拟存储器单元来补偿当相对大量的存储单元垂直地堆叠在半导体衬底上时使用电连接的多个垂直子串的过程伪像，否则会产生相对较差的功能性存储单元串系列。

34. 发明申请

US20100193861A1 Three-Dimensional Memory Device 有权
标题翻译：三维存储器件
公开(公告)号：US20100193861A1
公开(公告)日：2010-08-05
申请号：US12694339
申请日：2010-01-27
申请人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
发明人： Sunil Shim , Hansoo Kim , Jaehoon Jang , Jaehun Jeong
IPC分类号： H01L29/78
CPC分类号： H01L27/11551 , G11C16/0483 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.
摘要翻译：三维半导体器件包括：半导体衬底，以矩阵形式布置在半导体衬底上的垂直沟道结构;设置在半导体衬底处以与垂直沟道结构直接相连的P型半导体层;以及布置的公共源极线在垂直沟道结构之间的半导体衬底处。公共源极线可以与P型半导体层接触。

35. 发明授权

US08913433B2 Nonvolatile memory devices, read methods thereof and memory systems including the nonvolatile memory devices 有权
标题翻译：非易失性存储器件，其读取方法和包括非易失性存储器件的存储器系统
公开(公告)号：US08913433B2
公开(公告)日：2014-12-16
申请号：US13093320
申请日：2011-04-25
申请人： Kihyun Kim , Hansoo Kim , Jaehoon Jang , Sunil Shim , Chulmin Park
发明人： Kihyun Kim , Hansoo Kim , Jaehoon Jang , Sunil Shim , Chulmin Park
IPC分类号： G11C16/04 , G11C16/26 , G11C16/10 , H01L27/115 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , H01L27/115 , H01L27/11582
摘要： Reading methods of nonvolatile memory devices including a substrate and a plurality of memory cells which are stacked in a direction intersecting the substrate. The reading methods apply a bit line voltage to a plurality of bit lines and apply a first string selection line voltage to at least one selected string selection line. The reading methods apply a second string selection line voltage to at least one unselected string selection line and apply a read voltage to a plurality of word lines. The reading methods apply a first ground selection line voltage to at least one selected ground selection line and apply a second ground selection line voltage to at least one unselected ground selection line.
摘要翻译：非易失性存储器件的读取方法包括在与衬底交叉的方向上堆叠的衬底和多个存储单元。读取方法将位线电压施加到多个位线，并将第一串选择线电压施加到至少一个所选择的串选择线。读取方法将第二串选择线电压施加到至少一个未选择的串选择线，并将读电压施加到多个字线。读取方法将第一接地选择线电压施加到至少一个所选择的接地选择线，并将第二接地选择线电压施加到至少一个未选择的接地选择线。

36. 发明申请

US20140124846A1 SEMICONDUCTOR MEMORY DEVICES HAVING SELECTION TRANSISTORS WITH NONUNIFORM THRESHOLD VOLTAGE CHARACTERISTICS 审中-公开
标题翻译：具有非线性阈值电压特性的选择晶体管的半导体存储器件
公开(公告)号：US20140124846A1
公开(公告)日：2014-05-08
申请号：US14154834
申请日：2014-01-14
申请人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Su-Youn Yi , Jaehoon Jang , Sunghoi Hur
发明人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Su-Youn Yi , Jaehoon Jang , Sunghoi Hur
IPC分类号： H01L27/02
CPC分类号： H01L27/0207 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.
摘要翻译：提供了一种半导体存储器件。在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

37. 发明授权

US08603906B2 Method of forming a three-dimensional semiconductor memory device comprising sub-cells, terraced structures and strapping regions 有权
标题翻译：形成三维半导体存储器件的方法，其包括子单元，梯形结构和捆扎区域
公开(公告)号：US08603906B2
公开(公告)日：2013-12-10
申请号：US13779334
申请日：2013-02-27
申请人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
发明人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02365 , H01L21/02697 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.
摘要翻译：提供一种三维半导体存储器件。三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

38. 发明授权

US08395190B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US08395190B2
公开(公告)日：2013-03-12
申请号：US12943126
申请日：2010-11-10
申请人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
发明人： Sunil Shim , Sunghoi Hur , Hansoo Kim , Jaehoon Jang , Hoosung Cho
IPC分类号： H01L23/52
CPC分类号： H01L21/02365 , H01L21/02697 , H01L27/11565 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.
摘要翻译：提供一种三维半导体存储器件。三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。

39. 发明授权

US08319275B2 Integrated circuit memory devices having selection transistors with nonuniform threshold voltage characteristics 有权
标题翻译：具有选择晶体管的集成电路存储器件具有不均匀的阈值电压特性
公开(公告)号：US08319275B2
公开(公告)日：2012-11-27
申请号：US12698542
申请日：2010-02-02
申请人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Sunghoi Hur , Jaehoon Jang , Su-Youn Yi
发明人： Sunil Shim , Jaehun Jeong , Hansoo Kim , Sunghoi Hur , Jaehoon Jang , Su-Youn Yi
IPC分类号： H01L29/792 , H01L29/66 , H01L27/088
CPC分类号： H01L27/0207 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.
摘要翻译：提供了一种半导体存储器件。在半导体存储器件中，下部选择栅极控制限定在半导体衬底上的第一沟道区和限定在设置在半导体衬底上的有源图案的下部的第二沟道区。第一沟道区的第一阈值电压不同于第二沟道区的第二阈值电压。

40. 发明申请

US20120228712A1 NONVOLATILE MEMORY DEVICES 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120228712A1
公开(公告)日：2012-09-13
申请号：US13478482
申请日：2012-05-23
申请人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
发明人： Jaehun Jeong , Hansoo Kim , Jaehoon Jang , Hoosung Cho , Kyoung-Hoon Kim
IPC分类号： H01L27/088
CPC分类号： H01L27/11578 , H01L27/115 , H01L27/11517 , H01L27/11565 , H01L27/11582
摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
摘要翻译：具有三维结构的非易失性存储装置。非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

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