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31. 发明授权

US5901091A Bi-directional data input/output circuit of a synchronous memory device and the method for controlling the same 失效
标题翻译：同步存储器件的双向数据输入/输出电路及其控制方法
公开(公告)号：US5901091A
公开(公告)日：1999-05-04
申请号：US63371
申请日：1998-04-21
申请人： Jae Jin Lee
发明人： Jae Jin Lee
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409 , G11C11/4096 , G11C11/417 , G11C16/04 , G11C7/02 , G11C8/00
CPC分类号： G11C7/1048 , G11C11/4096 , G11C7/1006 , G11C7/22
摘要： There is disclosed a bidirectional data input/output circuit of a synchronous memory device and the method for controlling the same according to the present invention. The synchronous memory device according to the present invention is aimed at solving a data confusion problem generated when a write operation subsequent to a data read operation is performed in a data input/output line. Though the data line is a bidirectional bus data line by which an input/output is also performed, it can be applied to a circuit construction in which high and low potential data are inputted/outputted through an independent dedicated line. In addition, there is provided an internal buffer for inputting a write data into the memory device. The circuit according to the present invention further includes a memory for storing a data signal generated upon a read operation, when a read operation subsequent in time to a write operation is performed; and a device for selecting as a write data the opposite signal of the data signal generated upon a read operation when the two data lines both become active.
摘要翻译：公开了根据本发明的同步存储器件的双向数据输入/输出电路及其控制方法。根据本发明的同步存储装置旨在解决在数据输入/输出线中执行数据读取操作之后的写入操作时产生的数据混淆问题。虽然数据线是还进行输入/输出的双向总线数据线，但是它可以应用于通过独立专用线输入/输出高电平和低电位数据的电路结构。此外，提供了一种用于将写入数据输入到存储器件中的内部缓冲器。根据本发明的电路还包括一个存储器，用于当执行写入操作的时间之后的读取操作时，存储在读取操作时产生的数据信号; 以及用于当两个数据线都变为活动时，在读取操作时产生的数据信号的相反信号作为写数据选择的装置。

32. 发明授权

US5862144A Method for correcting a high frequency measurement error 失效
标题翻译：校正高频测量误差的方法
公开(公告)号：US5862144A
公开(公告)日：1999-01-19
申请号：US956913
申请日：1997-10-23
申请人： Chang Seok Lee , Ingab Hwang , Min Gun Kim , Jae Jin Lee , Kwang Eui Pyun
发明人： Chang Seok Lee , Ingab Hwang , Min Gun Kim , Jae Jin Lee , Kwang Eui Pyun
IPC分类号： G01R23/00 , G01R27/32 , G06F11/00
CPC分类号： G01R27/32
摘要： A method for correcting a high frequency measurement error which can exactly correct the high frequency measurement error even with the use of a standard devices of which characteristic have not been verified by calculating the characteristic impedance of the correction device from the characteristics of an auxiliary measuring device calculated by using a general error correction method, and calculating again the once calculated characteristics of the auxiliary measuring device. The method in accordance with the present invention comprises the steps of modelling an auxiliary measuring device used for measuring a high frequency charateristics of the device under test by two transmission lines connected in series between two terminals and a parasitic component connected in parallel between a junction of the two transmission lines and a ground; and moving a reference measurement point to the junction of the two transmission lines by using a phase angle of each transmission line and calculating a reference impedance at the terminal of the auxiliary measuring device to which an object to be measured is connected by using the difference of the resultant reflection coefficients of each port.
摘要翻译：一种用于校正高频测量误差的方法，即使使用通过从辅助测量装置的特性计算校正装置的特性阻抗尚未验证其特性的标准装置，也可以精确地校正高频测量误差通过使用通用误差校正方法计算，并再次计算辅助测量装置的一次计算的特性。根据本发明的方法包括以下步骤：对用于测量被测器件的高频特性的两个传输线串联连接在两个端子之间的辅助测量装置和在两个端子之间并联连接的寄生元件进行建模，两条传输线和一条地面; 并且通过使用每个传输线的相位角将参考测量点移动到两个传输线的结点，并且通过使用所述差异来计算被测量对象的辅助测量装置的端子处的基准阻抗每个端口的反射系数。

33. 发明授权

US5719810A Semiconductor memory device having cache memory function 失效
标题翻译：具有高速缓存存储功能的半导体存储器件
公开(公告)号：US5719810A
公开(公告)日：1998-02-17
申请号：US548212
申请日：1995-10-25
申请人： Jae Jin Lee , Seung Han Ahn
发明人： Jae Jin Lee , Seung Han Ahn
IPC分类号： G06F11/00 , G11C7/00 , G11C7/10 , G11C29/38
CPC分类号： G06F11/004 , G11C29/38 , G11C7/00 , G11C7/1078
摘要： A semiconductor memory device comprising a memory cell array for storing input data therein, a data output buffer for outputting the data stored in the memory cell array externally, an output terminal for transferring the output data from the data output buffer externally, a data input buffer for transferring the output data from the data output buffer to the memory cell array, a data register for temporarily storing the transferred data from the data input buffer, and a multiplexer connected among the memory cell array, the data register and the data output buffer, for selecting one of the data stored in the memory cell array and the data stored in the data register and transferring the selected data to the data output buffer. In the normal case, the multiplexer selects the data stored in the memory cell array and transfers the selected data to the data output buffer. In a specific case where the input data to the memory cell array have the same values or a regularity, the multiplexer selects the data stored in the data register and transfers the selected data to the data output buffer.
摘要翻译：一种半导体存储器件，包括用于存储输入数据的存储单元阵列，用于将外部存储在存储单元阵列中的数据输出的数据输出缓冲器，用于从外部从数据输出缓冲器传送输出数据的输出端，数据输入缓冲器用于将输出数据从数据输出缓冲器传送到存储单元阵列，用于临时存储来自数据输入缓冲器的传送数据的数据寄存器和连接在存储单元阵列，数据寄存器和数据输出缓冲器之间的多路复用器，用于选择存储在存储单元阵列中的数据之一和存储在数据寄存器中的数据，并将所选择的数据传送到数据输出缓冲器。在正常情况下，多路复用器选择存储在存储单元阵列中的数据，并将选择的数据传送到数据输出缓冲器。在存储单元阵列的输入数据具有相同的值或规则性的特定情况下，多路复用器选择存储在数据寄存器中的数据并将选择的数据传送到数据输出缓冲器。

34. 发明授权

US5689396A Signal input unit for semiconductor memory device 失效
标题翻译：半导体存储器件的信号输入单元
公开(公告)号：US5689396A
公开(公告)日：1997-11-18
申请号：US559605
申请日：1995-11-20
申请人： Jae Jin Lee
发明人： Jae Jin Lee
IPC分类号： H01L27/04 , H01L27/02 , H03K17/00 , H03K17/04 , H03K17/08 , H03K19/003 , H03K19/0175 , H02H9/00
CPC分类号： H01L27/0266 , H03K19/00315
摘要： A signal input unit for a semiconductor memory device comprising a signal input terminal, an electrostatic discharge protection circuit for discharging an electrostatic signal of high level from the input terminal to a ground voltage source, a signal transfer circuit connected in parallel to the electrostatic discharge protection circuit, for switching a normal input signal from the input terminal, a signal transfer control circuit for controlling a switching operation of the signal transfer circuit, and a signal input circuit for buffering an output signal from the electrostatic discharge protection circuit or the signal transfer circuit and transferring the buffered signal to an internal circuit of the semiconductor memory device. The electrostatic discharge protection circuit sufficiently discharges the external electrostatic signal to the ground voltage source in a standby mode of the semiconductor memory device. The signal transfer circuit is connected in parallel to the electrostatic discharge protection circuit so that the normal input signal can be transferred directly to the signal input circuit in an operation mode of the semiconductor memory device with no delay by the electrostatic discharge protection circuit. Therefore, a signal delay can be prevented.
摘要翻译：一种用于半导体存储器件的信号输入单元，包括信号输入端子，用于将高电平的静电信号从输入端子放电到地电压源的静电放电保护电路，与静电放电保护并联连接的信号传输电路电路，用于切换来自输入端子的正常输入信号，用于控制信号传送电路的切换操作的信号传送控制电路，以及用于缓冲来自静电放电保护电路或信号传输电路的输出信号的信号输入电路以及将缓冲信号传送到半导体存储器件的内部电路。在半导体存储器件的待机模式下，静电放电保护电路将外部静电信号充分地放电到地电压源。信号传送电路并联连接到静电放电保护电路，使得在半导体存储器件的操作模式下，通过静电放电保护电路不会将正常输入信号直接传送到信号输入电路。因此，可以防止信号延迟。

35. 发明申请

US20140110745A1 LIGHT EMITTING DIODE PACKAGE 有权
标题翻译：发光二极管封装
公开(公告)号：US20140110745A1
公开(公告)日：2014-04-24
申请号：US14124974
申请日：2012-02-02
申请人： Jae Jin Lee , Sung Ho Choi , Duk In Kang
发明人： Jae Jin Lee , Sung Ho Choi , Duk In Kang
IPC分类号： H01L33/62
CPC分类号： H01L33/62 , H01L27/32 , H01L33/642 , H01L33/647 , H01L51/50 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： An LED package includes a lead frame, a housing part, and a lead heat dissipating part. The lead frame includes a first lead mounting an LED chip and a second lead spaced apart from the first lead. The housing part covers a portion of the lead frame and includes an opening part for exposing the LED chip, a first side corresponding to a support side contacting the first lead and the second lead, and a second side opposite to the first side. The lead heat dissipating part is extended from the first lead and exposed partially to the first side of the housing part. Herein, the first side of the housing part is thicker than the second side.
摘要翻译： LED封装包括引线框架，壳体部分和引线散热部件。引线框架包括安装LED芯片的第一引线和与第一引线间隔开的第二引线。壳体部分覆盖引线框架的一部分并且包括用于暴露LED芯片的开口部分，对应于接触第一引线和第二引线的支撑侧的第一侧和与第一侧相对的第二侧。引线散热部分从第一引线延伸并部分暴露于壳体部分的第一侧。这里，壳体部分的第一侧比第二侧厚。

36. 发明授权

US08559524B2 Video decoding apparatus and method based on a data and function splitting scheme 有权
标题翻译：基于数据和功能分割方案的视频解码装置和方法
公开(公告)号：US08559524B2
公开(公告)日：2013-10-15
申请号：US12837022
申请日：2010-07-15
申请人： Jae Jin Lee , Moo Kyoung Chung , Kyung Su Kim , Jun Young Lee , Seong Mo Park , Nak Woong Eum
发明人： Jae Jin Lee , Moo Kyoung Chung , Kyung Su Kim , Jun Young Lee , Seong Mo Park , Nak Woong Eum
IPC分类号： H04N7/26
CPC分类号： H04N19/436 , H04N19/44 , H04N19/61
摘要： A video decoding apparatus and method based on a data and function splitting scheme are disclosed. The video decoding apparatus based on a data and function splitting scheme includes a variable length decoding unit performing variable length decoding and parsing on a bit stream to acquire residual data and a decoding parameter, and splitting the residual data and the decoding parameter by row; and N (N is a natural number of 2 or larger) number of clusters splitting dequantization and inverse discrete cosine transform (IDCT), motion vector prediction, intra prediction and motion compensation, video restoration, and deblocking function into M number of functions, acquiring the residual data, the decoding parameter, and macroblock (MB) processing information of an upper cluster by column, and splitting the information acquired by column into M number of functions to process the same.
摘要翻译：公开了一种基于数据和功能分解方案的视频解码装置和方法。基于数据和功能分割方案的视频解码装置包括：可变长度解码单元，对比特流执行可变长度解码和解析以获取残差数据和解码参数，并且逐行分割残留数据和解码参数; 并且N（N是2或更大的自然数）将数量分解解量化和逆离散余弦变换（IDCT），运动矢量预测，帧内预测和运动补偿，视频恢复和去块功能的簇数分为M个函数，获取按照列逐列的残差数据，解码参数和宏块（MB）处理信息，并将通过列获取的信息拆分为M个函数以进行处理。

37. 发明授权

US08519734B2 Semiconductor apparatus, method for assigning chip IDs therein, and method for setting chip IDs thereof 有权
标题翻译：半导体装置，其中分配芯片ID的方法及其芯片ID的设定方法
公开(公告)号：US08519734B2
公开(公告)日：2013-08-27
申请号：US13162676
申请日：2011-06-17
申请人： Chun Seok Jeong , Jae Jin Lee
发明人： Chun Seok Jeong , Jae Jin Lee
IPC分类号： H03K19/003
CPC分类号： G11C7/20 , G11C29/883 , G11C2029/4402 , H01L2224/16
摘要： A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code.
摘要翻译：具有第一和第二芯片的半导体装置包括设置在第一芯片中的第一操作单元，并且被配置为根据第一修复信号对初始码执行预定的算术运算，并生成第一操作码; 以及第二操作单元，设置在所述第二芯片中，并且被配置为根据第二修复信号对所述第一操作码执行所述预定算术运算，并生成第二操作码。

38. 发明授权

US08358555B2 Fuse circuit and control method thereof 有权
标题翻译：保险丝电路及其控制方法
公开(公告)号：US08358555B2
公开(公告)日：2013-01-22
申请号：US12835978
申请日：2010-07-14
申请人： Jin Youp Cha , Jae Jin Lee
发明人： Jin Youp Cha , Jae Jin Lee
IPC分类号： G11C17/18 , G11C17/00 , H01H85/00
CPC分类号： G11C17/16 , G11C29/785
摘要： A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.
摘要翻译：熔丝电路包括配置成执行熔丝编程并响应于熔丝编程信号产生熔丝信号的多个熔丝组，以及配置成根据编程电压的电平产生熔丝编程信号的熔丝控制单元。

39. 发明授权

US08035146B2 Nonvolatile ferroelectric memory device 有权
标题翻译：非易失性铁电存储器件
公开(公告)号：US08035146B2
公开(公告)日：2011-10-11
申请号：US12820092
申请日：2010-06-21
申请人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
发明人： Hee Bok Kang , Jin Hong Ahn , Jae Jin Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , G11C11/22 , H01L21/84 , H01L27/11585 , H01L27/1159 , H01L29/6684 , H01L29/78391 , H01L29/7841
摘要： A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers.
摘要翻译：非易失性铁电存储器件包括多个单元阵列，其中多个单元阵列中的每一个包括：底部字线; 分别形成在底部字线上的多个绝缘层; 浮动沟道层，包括位于所述多个绝缘层上的多个沟道区和与所述多个沟道区交替电连接的多个漏极和源极区; 分别形成在所述浮动沟道层的所述多个沟道区上的多个铁电层; 以及分别形成在多个铁电体层上的多个字线。根据多个铁电层的极性状态，单元阵列通过对多个沟道区域引起不同的沟道电阻来读取和写入多个数据。

40. 发明申请

US20110187429A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20110187429A1
公开(公告)日：2011-08-04
申请号：US12838332
申请日：2010-07-16
申请人： Sang Jin BYEON , Jae Jin Lee
发明人： Sang Jin BYEON , Jae Jin Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.
摘要翻译：半导体装置具有堆叠在其中的多个芯片。用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。

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